Wireless neural signal acquisition with single low-power integrated circuit

Reid R. Harrison, Ryan J. Kier, Bradley Greger, Florian Solzbacher, Cynthia A. Chestek, Vikash Gilja, Paul Nuyujukian, Stephen I. Ryu, Krishna V. Shenoy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers and a 10-bit ADC and 902-928 MHz FSK transmitter. Neural signals from one amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power receive coil and a 100-nF capacitor.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1748-1751
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

Fingerprint

Power integrated circuits
Frequency shift keying
Telecommunication links
Integrated circuits
Clocks
Transmitters
Capacitors

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Harrison, R. R., Kier, R. J., Greger, B., Solzbacher, F., Chestek, C. A., Gilja, V., ... Shenoy, K. V. (2008). Wireless neural signal acquisition with single low-power integrated circuit. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1748-1751). [4541776] https://doi.org/10.1109/ISCAS.2008.4541776

Wireless neural signal acquisition with single low-power integrated circuit. / Harrison, Reid R.; Kier, Ryan J.; Greger, Bradley; Solzbacher, Florian; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen I.; Shenoy, Krishna V.

Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 1748-1751 4541776.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harrison, RR, Kier, RJ, Greger, B, Solzbacher, F, Chestek, CA, Gilja, V, Nuyujukian, P, Ryu, SI & Shenoy, KV 2008, Wireless neural signal acquisition with single low-power integrated circuit. in Proceedings - IEEE International Symposium on Circuits and Systems., 4541776, pp. 1748-1751, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 5/18/08. https://doi.org/10.1109/ISCAS.2008.4541776
Harrison RR, Kier RJ, Greger B, Solzbacher F, Chestek CA, Gilja V et al. Wireless neural signal acquisition with single low-power integrated circuit. In Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 1748-1751. 4541776 https://doi.org/10.1109/ISCAS.2008.4541776
Harrison, Reid R. ; Kier, Ryan J. ; Greger, Bradley ; Solzbacher, Florian ; Chestek, Cynthia A. ; Gilja, Vikash ; Nuyujukian, Paul ; Ryu, Stephen I. ; Shenoy, Krishna V. / Wireless neural signal acquisition with single low-power integrated circuit. Proceedings - IEEE International Symposium on Circuits and Systems. 2008. pp. 1748-1751
@inproceedings{26764b4af340400bb260372c3bec46eb,
title = "Wireless neural signal acquisition with single low-power integrated circuit",
abstract = "We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers and a 10-bit ADC and 902-928 MHz FSK transmitter. Neural signals from one amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power receive coil and a 100-nF capacitor.",
author = "Harrison, {Reid R.} and Kier, {Ryan J.} and Bradley Greger and Florian Solzbacher and Chestek, {Cynthia A.} and Vikash Gilja and Paul Nuyujukian and Ryu, {Stephen I.} and Shenoy, {Krishna V.}",
year = "2008",
doi = "10.1109/ISCAS.2008.4541776",
language = "English (US)",
isbn = "9781424416844",
pages = "1748--1751",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - Wireless neural signal acquisition with single low-power integrated circuit

AU - Harrison, Reid R.

AU - Kier, Ryan J.

AU - Greger, Bradley

AU - Solzbacher, Florian

AU - Chestek, Cynthia A.

AU - Gilja, Vikash

AU - Nuyujukian, Paul

AU - Ryu, Stephen I.

AU - Shenoy, Krishna V.

PY - 2008

Y1 - 2008

N2 - We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers and a 10-bit ADC and 902-928 MHz FSK transmitter. Neural signals from one amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power receive coil and a 100-nF capacitor.

AB - We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers and a 10-bit ADC and 902-928 MHz FSK transmitter. Neural signals from one amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power receive coil and a 100-nF capacitor.

UR - http://www.scopus.com/inward/record.url?scp=51749118026&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51749118026&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2008.4541776

DO - 10.1109/ISCAS.2008.4541776

M3 - Conference contribution

AN - SCOPUS:51749118026

SN - 9781424416844

SP - 1748

EP - 1751

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -