Where is the Achilles heel under circuit aging

Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
PublisherIEEE Computer Society
Pages278-279
Number of pages2
ISBN (Electronic)9781479937639
DOIs
StatePublished - Sep 18 2014
Event2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States
Duration: Jul 9 2014Jul 11 2014

Other

Other2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
CountryUnited States
CityTampa
Period7/9/147/11/14

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Keywords

  • BTI
  • DVS
  • HCI
  • asymmetric aging
  • bias runaway
  • circuit aging

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Sutaria, K., Ramkumar, A., Zhu, R., & Cao, Y. (2014). Where is the Achilles heel under circuit aging. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI (pp. 278-279). [6903375] IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2014.106