Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

M. Goryll; J. Moers; St Trellenkamp; L. Vescan; M. Marso; P. Kordoš; H. Lüth

doi:10.1016/S1386-9477(03)00287-X

Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

M. Goryll, J. Moers, St Trellenkamp, L. Vescan, M. Marso, P. Kordoš, H. Lüth

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.

Original language	English (US)
Pages (from-to)	18-22
Number of pages	5
Journal	Physica E: Low-Dimensional Systems and Nanostructures
Volume	19
Issue number	1-2
DOIs	https://doi.org/10.1016/S1386-9477(03)00287-X
State	Published - Jul 2003
Externally published	Yes
Event	Fourth International Symposium on Nanostructures and Mesoscopi - Tempe, AZ, United States Duration: Feb 17 2003 → Feb 21 2003

Keywords

Gate oxide
Low temperature oxidation
Vertical field-effect transistor

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics

Access to Document

10.1016/S1386-9477(03)00287-X

Cite this

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title = "Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors",

abstract = "In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.",

keywords = "Gate oxide, Low temperature oxidation, Vertical field-effect transistor",

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year = "2003",

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doi = "10.1016/S1386-9477(03)00287-X",

language = "English (US)",

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note = "Fourth International Symposium on Nanostructures and Mesoscopi ; Conference date: 17-02-2003 Through 21-02-2003",

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TY - JOUR

T1 - Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

AU - Goryll, M.

AU - Moers, J.

AU - Trellenkamp, St

AU - Vescan, L.

AU - Marso, M.

AU - Kordoš, P.

AU - Lüth, H.

PY - 2003/7

Y1 - 2003/7

N2 - In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.

AB - In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.

KW - Gate oxide

KW - Low temperature oxidation

KW - Vertical field-effect transistor

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U2 - 10.1016/S1386-9477(03)00287-X

DO - 10.1016/S1386-9477(03)00287-X

M3 - Conference article

AN - SCOPUS:0041508692

SN - 1386-9477

VL - 19

SP - 18

EP - 22

JO - Physica E: Low-Dimensional Systems and Nanostructures

JF - Physica E: Low-Dimensional Systems and Nanostructures

IS - 1-2

T2 - Fourth International Symposium on Nanostructures and Mesoscopi

Y2 - 17 February 2003 through 21 February 2003

ER -

Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

Abstract

Keywords

ASJC Scopus subject areas

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