Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

M. Goryll, J. Moers, St Trellenkamp, L. Vescan, M. Marso, P. Kordoš, H. Lüth

Research output: Contribution to journalConference articlepeer-review

Abstract

In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.

Original languageEnglish (US)
Pages (from-to)18-22
Number of pages5
JournalPhysica E: Low-Dimensional Systems and Nanostructures
Volume19
Issue number1-2
DOIs
StatePublished - Jul 1 2003
Externally publishedYes
EventFourth International Symposium on Nanostructures and Mesoscopi - Tempe, AZ, United States
Duration: Feb 17 2003Feb 21 2003

Keywords

  • Gate oxide
  • Low temperature oxidation
  • Vertical field-effect transistor

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

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