Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni; Deepak Vinayak Kadetotad; Jae-sun Seo; Bipin Rajendran

doi:10.1109/SISPAD.2018.8551667

Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Jae-sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge ₂ Sb ₂ Te ₅ , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.

Original language	English (US)
Title of host publication	SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	369-373
Number of pages	5
ISBN (Electronic)	9781538667880
DOIs	https://doi.org/10.1109/SISPAD.2018.8551667
State	Published - Nov 28 2018
Event	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 - Austin, United States Duration: Sep 24 2018 → Sep 26 2018

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2018-September

Other

Other	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018
Country/Territory	United States
City	Austin
Period	9/24/18 → 9/26/18

Keywords

Phase change memory
Verilog-A
chalcogenide
well-posed model

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Modeling and Simulation

Access to Document

10.1109/SISPAD.2018.8551667

Cite this

Kulkarni, S. R., Kadetotad, D. V., Seo, J., & Rajendran, B. (2018). Well-Posed Verilog-A Compact Model for Phase Change Memory. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings (pp. 369-373). Article 8551667 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2018.8551667

Well-Posed Verilog-A Compact Model for Phase Change Memory. / Kulkarni, Shruti R.; Kadetotad, Deepak Vinayak; Seo, Jae-sun et al.
SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 369-373 8551667 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kulkarni, SR, Kadetotad, DV, Seo, J & Rajendran, B 2018, Well-Posed Verilog-A Compact Model for Phase Change Memory. in SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings., 8551667, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2018-September, Institute of Electrical and Electronics Engineers Inc., pp. 369-373, 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018, Austin, United States, 9/24/18. https://doi.org/10.1109/SISPAD.2018.8551667

Kulkarni SR, Kadetotad DV, Seo J, Rajendran B. Well-Posed Verilog-A Compact Model for Phase Change Memory. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 369-373. 8551667. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2018.8551667

Kulkarni, Shruti R. ; Kadetotad, Deepak Vinayak ; Seo, Jae-sun et al. / Well-Posed Verilog-A Compact Model for Phase Change Memory. SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 369-373 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

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title = "Well-Posed Verilog-A Compact Model for Phase Change Memory",

abstract = " In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge 2 Sb 2 Te 5 , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.",

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Well-Posed Verilog-A Compact Model for Phase Change Memory

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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