Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Jae-sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge 2 Sb 2 Te 5 , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.

Original languageEnglish (US)
Title of host publicationSISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages369-373
Number of pages5
ISBN (Electronic)9781538667880
DOIs
StatePublished - Nov 28 2018
Event2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 - Austin, United States
Duration: Sep 24 2018Sep 26 2018

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2018-September

Other

Other2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018
CountryUnited States
CityAustin
Period9/24/189/26/18

Keywords

  • Phase change memory
  • Verilog-A
  • chalcogenide
  • well-posed model

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

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