Abstract
Several types of as-received and complementary metal oxide semiconductor (CMOS) thermal simulated 100 mm wafers were used for warpage study under different annealing conditions. The results indicated that as-received wafers showed little increase in warpage up to 1000°C furnace temperature and 61.0 cm/min insertion rate. For the CMOS thermal simulation processed wafers, both the prior amount of oxygen precipitation, Δ[Oi], where Δ[Oi] is the decrease in interstitial oxygen concentration, and bulk microdefect morphology affected warpage. For Δ[Oi] less than ca. 26 ppma, wafers with predominantly octahedral precipitates without associated dislocations plus a low density of small plate-type and dot-like precipitates underwent much less warpage than wafers with predominantly large octahedral precipitates and precipitate-dislocation-complexes (PDCs). When the Δ[Oi] was higher than 26 ppma, the defects consisted of a high density of large octahedral-shaped precipitates and PDCs and thus warpage became inevitable.
Original language | English (US) |
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Pages (from-to) | 1856-1862 |
Number of pages | 7 |
Journal | Journal of the Electrochemical Society |
Volume | 141 |
Issue number | 7 |
DOIs | |
State | Published - Jul 1994 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Renewable Energy, Sustainability and the Environment
- Surfaces, Coatings and Films
- Electrochemistry
- Materials Chemistry