Wafer-level RF test and DfT for VCO modulating transceiver architecures

Sule Ozev, Christian Olgaard

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Traditionally, radio frequency (RF) paths are bypassed during wafer sort due to the high cost of RF testing. Increasing packaging costs, however, result in a need for a more thorough wafer-level testing including the RF path. In this paper, we propose a loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level. These methods are applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator(VCO). Experimental results using a Bluetooth platform and considering a variety of defects confirm the viability of the approach.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE VLSI Test Symposium
Pages217-222
Number of pages6
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings - 22nd IEEE VLSI Test Symposium - Napa Valley, CA, United States
Duration: Apr 25 2004Apr 29 2004

Other

OtherProceedings - 22nd IEEE VLSI Test Symposium
CountryUnited States
CityNapa Valley, CA
Period4/25/044/29/04

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Wafer-level RF test and DfT for VCO modulating transceiver architecures'. Together they form a unique fingerprint.

Cite this