Voltage-frequency island partitioning for GALS-based networks-on-chip

Umit Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

117 Citations (Scopus)

Abstract

Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages110-115
Number of pages6
DOIs
StatePublished - 2007
Externally publishedYes
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

Fingerprint

Electric potential
Energy utilization
Threshold voltage
Network-on-chip
Field programmable gate arrays (FPGA)
Clocks
Electric power utilization

Keywords

  • GALS
  • Multi-processor systems
  • Networks-on-chip
  • Voltage-frequency island

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Ogras, U., Marculescu, R., Choudhary, P., & Marculescu, D. (2007). Voltage-frequency island partitioning for GALS-based networks-on-chip. In Proceedings - Design Automation Conference (pp. 110-115). [4261154] https://doi.org/10.1109/DAC.2007.375135

Voltage-frequency island partitioning for GALS-based networks-on-chip. / Ogras, Umit; Marculescu, Radu; Choudhary, Puru; Marculescu, Diana.

Proceedings - Design Automation Conference. 2007. p. 110-115 4261154.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ogras, U, Marculescu, R, Choudhary, P & Marculescu, D 2007, Voltage-frequency island partitioning for GALS-based networks-on-chip. in Proceedings - Design Automation Conference., 4261154, pp. 110-115, 2007 44th ACM/IEEE Design Automation Conference, DAC'07, San Diego, CA, United States, 6/4/07. https://doi.org/10.1109/DAC.2007.375135
Ogras U, Marculescu R, Choudhary P, Marculescu D. Voltage-frequency island partitioning for GALS-based networks-on-chip. In Proceedings - Design Automation Conference. 2007. p. 110-115. 4261154 https://doi.org/10.1109/DAC.2007.375135
Ogras, Umit ; Marculescu, Radu ; Choudhary, Puru ; Marculescu, Diana. / Voltage-frequency island partitioning for GALS-based networks-on-chip. Proceedings - Design Automation Conference. 2007. pp. 110-115
@inproceedings{930f77666121443f8e8d208051f52a5f,
title = "Voltage-frequency island partitioning for GALS-based networks-on-chip",
abstract = "Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40{\%} savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.",
keywords = "GALS, Multi-processor systems, Networks-on-chip, Voltage-frequency island",
author = "Umit Ogras and Radu Marculescu and Puru Choudhary and Diana Marculescu",
year = "2007",
doi = "10.1109/DAC.2007.375135",
language = "English (US)",
isbn = "1595936270",
pages = "110--115",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Voltage-frequency island partitioning for GALS-based networks-on-chip

AU - Ogras, Umit

AU - Marculescu, Radu

AU - Choudhary, Puru

AU - Marculescu, Diana

PY - 2007

Y1 - 2007

N2 - Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

AB - Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

KW - GALS

KW - Multi-processor systems

KW - Networks-on-chip

KW - Voltage-frequency island

UR - http://www.scopus.com/inward/record.url?scp=34547254666&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547254666&partnerID=8YFLogxK

U2 - 10.1109/DAC.2007.375135

DO - 10.1109/DAC.2007.375135

M3 - Conference contribution

AN - SCOPUS:34547254666

SN - 1595936270

SN - 9781595936271

SP - 110

EP - 115

BT - Proceedings - Design Automation Conference

ER -