TY - GEN
T1 - Voltage-frequency island partitioning for GALS-based networks-on-chip
AU - Ogras, Umit Y.
AU - Marculescu, Radu
AU - Choudhary, Puru
AU - Marculescu, Diana
PY - 2007
Y1 - 2007
N2 - Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.
AB - Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.
KW - GALS
KW - Multi-processor systems
KW - Networks-on-chip
KW - Voltage-frequency island
UR - http://www.scopus.com/inward/record.url?scp=34547254666&partnerID=8YFLogxK
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U2 - 10.1109/DAC.2007.375135
DO - 10.1109/DAC.2007.375135
M3 - Conference contribution
AN - SCOPUS:34547254666
SN - 1595936270
SN - 9781595936271
T3 - Proceedings - Design Automation Conference
SP - 110
EP - 115
BT - 2007 44th ACM/IEEE Design Automation Conference, DAC'07
T2 - 2007 44th ACM/IEEE Design Automation Conference, DAC'07
Y2 - 4 June 2007 through 8 June 2007
ER -