Abstract
Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fact that power consumption is a quadratic function of the voltage, while the speed is a linear function. In this paper, we show how voltage scaling can be scheduled to reduce energy usage while still meeting real-time deadlines.
Original language | English (US) |
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Pages (from-to) | 1586-1593 |
Number of pages | 8 |
Journal | IEEE Transactions on Computers |
Volume | 52 |
Issue number | 12 |
DOIs | |
State | Published - Dec 2003 |
Keywords
- Dynamic voltage scaling
- Power-aware computing
- Real-time systems
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics