VLSI implementation of adaptive bit/serial IIR filters

Rajeev Badyal, Sayfe Kiaei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.

Original languageEnglish (US)
Title of host publicationIEEE Pacific RIM Conf Commun Comput Signal Process
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages650-652
Number of pages3
StatePublished - 1989
Externally publishedYes
EventIEEE Pacific RIM Conference on Communications, Computers and Signal Processing - Victoria, BC, Canada
Duration: Jun 1 1989Jun 2 1989

Other

OtherIEEE Pacific RIM Conference on Communications, Computers and Signal Processing
CityVictoria, BC, Canada
Period6/1/896/2/89

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Badyal, R., & Kiaei, S. (1989). VLSI implementation of adaptive bit/serial IIR filters. In Anon (Ed.), IEEE Pacific RIM Conf Commun Comput Signal Process (pp. 650-652). Publ by IEEE.