VLSI design of multi-rate arrays for DSP algorithm

Aihua Li, Sayfe Kiaei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Multirate arrays where the data transmission rate at different paths varies are introduced. Using a multirate clock, transparent data or data with small delays are propagated K times faster than the computed data, achieving a speedup of a factor of K as compared to systolic arrays. A new synthesis method for a class of nonuniform recurrence equations named DURE (directional uniform recurrence equations) for multirate arrays is introduced. The synthesis method consists of 1) obtaining the DURE from the initial algorithm and 2) finding the symmetric plane, the schedule vector, and the projection vector.

Original languageEnglish (US)
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
PublisherPubl by IEEE
Pages1049-1052
Number of pages4
Volume2
StatePublished - 1990
Externally publishedYes
Event1990 International Conference on Acoustics, Speech, and Signal Processing: Speech Processing 2, VLSI, Audio and Electroacoustics Part 2 (of 5) - Albuquerque, New Mexico, USA
Duration: Apr 3 1990Apr 6 1990

Other

Other1990 International Conference on Acoustics, Speech, and Signal Processing: Speech Processing 2, VLSI, Audio and Electroacoustics Part 2 (of 5)
CityAlbuquerque, New Mexico, USA
Period4/3/904/6/90

Fingerprint

very large scale integration
Systolic arrays
systolic arrays
Data communication systems
Clocks
data transmission
synthesis
schedules
clocks
projection

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

Cite this

Li, A., & Kiaei, S. (1990). VLSI design of multi-rate arrays for DSP algorithm. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (Vol. 2, pp. 1049-1052). Publ by IEEE.

VLSI design of multi-rate arrays for DSP algorithm. / Li, Aihua; Kiaei, Sayfe.

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. Vol. 2 Publ by IEEE, 1990. p. 1049-1052.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, A & Kiaei, S 1990, VLSI design of multi-rate arrays for DSP algorithm. in ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. vol. 2, Publ by IEEE, pp. 1049-1052, 1990 International Conference on Acoustics, Speech, and Signal Processing: Speech Processing 2, VLSI, Audio and Electroacoustics Part 2 (of 5), Albuquerque, New Mexico, USA, 4/3/90.
Li A, Kiaei S. VLSI design of multi-rate arrays for DSP algorithm. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. Vol. 2. Publ by IEEE. 1990. p. 1049-1052
Li, Aihua ; Kiaei, Sayfe. / VLSI design of multi-rate arrays for DSP algorithm. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. Vol. 2 Publ by IEEE, 1990. pp. 1049-1052
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