VLSI design of dynamically reconfigurable array processor-DRAP

Sayfe Kiaei, Jaisimha K. Durgam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.

Original languageEnglish (US)
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Editors Anon
PublisherPubl by IEEE
Pages2484-2488
Number of pages5
Volume4
StatePublished - 1989
Externally publishedYes
Event1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland
Duration: May 23 1989May 26 1989

Other

Other1989 International Conference on Acoustics, Speech, and Signal Processing
CityGlasgow, Scotland
Period5/23/895/26/89

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

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  • Cite this

    Kiaei, S., & Durgam, J. K. (1989). VLSI design of dynamically reconfigurable array processor-DRAP. In Anon (Ed.), ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (Vol. 4, pp. 2484-2488). Publ by IEEE.