Abstract
A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.
Original language | English (US) |
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Title of host publication | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
Editors | Anon |
Publisher | Publ by IEEE |
Pages | 2484-2488 |
Number of pages | 5 |
Volume | 4 |
State | Published - 1989 |
Externally published | Yes |
Event | 1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland Duration: May 23 1989 → May 26 1989 |
Other
Other | 1989 International Conference on Acoustics, Speech, and Signal Processing |
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City | Glasgow, Scotland |
Period | 5/23/89 → 5/26/89 |
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering
- Acoustics and Ultrasonics