VLSI circuit of lamprey unit pattern generator

Elizabeth J. Brauer, Ranu Jung, Brett Thompsen, James Abbas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The purpose of this research is to develop an analog VLSI electronic circuit that mimics the behavior of the biological lamprey spinal cord. The lamprey is an eel-like lower vertegrate with a relatively simple nervous system. The pattern generator for locomotion is distributed along the 100 spinal segments of the lamprey spinal cord and can be treated as a chain of coupled unit Pattern Generators (uPG) with oscillatory properties. In this work, we consider a 4 neuron uPG model. Bifurcation analysis of this model indicates a wide range of behaviors. In addition, a CMOS analog integrated circuit has been designed, fabricated, and tested which models the biological lamprey unit Pattern Generator. Measurement results show that the electronic circuit behavior is qualitatively similar to that of the numerical model.

Original languageEnglish (US)
Title of host publicationProceedings of the International Joint Conference on Neural Networks
Place of PublicationUnited States
PublisherIEEE
Pages2319-2322
Number of pages4
Volume4
StatePublished - 1999
Externally publishedYes
EventInternational Joint Conference on Neural Networks (IJCNN'99) - Washington, DC, USA
Duration: Jul 10 1999Jul 16 1999

Other

OtherInternational Joint Conference on Neural Networks (IJCNN'99)
CityWashington, DC, USA
Period7/10/997/16/99

Fingerprint

VLSI circuits
CMOS integrated circuits
Networks (circuits)
Neurology
Neurons
Numerical models

ASJC Scopus subject areas

  • Software

Cite this

Brauer, E. J., Jung, R., Thompsen, B., & Abbas, J. (1999). VLSI circuit of lamprey unit pattern generator. In Proceedings of the International Joint Conference on Neural Networks (Vol. 4, pp. 2319-2322). United States: IEEE.

VLSI circuit of lamprey unit pattern generator. / Brauer, Elizabeth J.; Jung, Ranu; Thompsen, Brett; Abbas, James.

Proceedings of the International Joint Conference on Neural Networks. Vol. 4 United States : IEEE, 1999. p. 2319-2322.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, EJ, Jung, R, Thompsen, B & Abbas, J 1999, VLSI circuit of lamprey unit pattern generator. in Proceedings of the International Joint Conference on Neural Networks. vol. 4, IEEE, United States, pp. 2319-2322, International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, USA, 7/10/99.
Brauer EJ, Jung R, Thompsen B, Abbas J. VLSI circuit of lamprey unit pattern generator. In Proceedings of the International Joint Conference on Neural Networks. Vol. 4. United States: IEEE. 1999. p. 2319-2322
Brauer, Elizabeth J. ; Jung, Ranu ; Thompsen, Brett ; Abbas, James. / VLSI circuit of lamprey unit pattern generator. Proceedings of the International Joint Conference on Neural Networks. Vol. 4 United States : IEEE, 1999. pp. 2319-2322
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