TY - GEN
T1 - VLSI chip-set for affine-based video compression
AU - Fatemi, Omid
AU - Panchanathan, Sethuraman
PY - 1996/1/1
Y1 - 1996/1/1
N2 - A crucial operation in image and video processing applications is affine transforms. Typical applications of affine transforms include fractal block coding, camera operation detection, affine motion estimation, etc. Affine transforms involve complex operations and are hence difficult to implement in real-time. In this paper, we present a novel architecture for real-time implementation of affine transforms. First, we derive two fundamental operations from affine transforms and then propose an efficient method of implementing these operations. As an example of the application of ATP (Affine Transform Processor), we propose a high performance video compression algorithm mapped onto the proposed architecture. This algorithm is based on combined affine transform and vector quantization (ATVQ), where the infra-frame and inter-frame redundancy in the video sequence are exploited through piecewise self-similarity on a block-wise basis within a frame and between frames. ATVQ has the advantages of superior coding performance at a significantly reduced computational complexity. ATVQ has been mapped onto the ATP and real-time execution is demonstrated using a VHDL (VHSIC Hardware Description Language) implementation of ATP.
AB - A crucial operation in image and video processing applications is affine transforms. Typical applications of affine transforms include fractal block coding, camera operation detection, affine motion estimation, etc. Affine transforms involve complex operations and are hence difficult to implement in real-time. In this paper, we present a novel architecture for real-time implementation of affine transforms. First, we derive two fundamental operations from affine transforms and then propose an efficient method of implementing these operations. As an example of the application of ATP (Affine Transform Processor), we propose a high performance video compression algorithm mapped onto the proposed architecture. This algorithm is based on combined affine transform and vector quantization (ATVQ), where the infra-frame and inter-frame redundancy in the video sequence are exploited through piecewise self-similarity on a block-wise basis within a frame and between frames. ATVQ has the advantages of superior coding performance at a significantly reduced computational complexity. ATVQ has been mapped onto the ATP and real-time execution is demonstrated using a VHDL (VHSIC Hardware Description Language) implementation of ATP.
UR - http://www.scopus.com/inward/record.url?scp=0029718007&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029718007&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0029718007
SN - 0819420425
SN - 9780819420428
T3 - Proceedings of SPIE - The International Society for Optical Engineering
SP - 233
EP - 242
BT - Proceedings of SPIE - The International Society for Optical Engineering
A2 - Bhaskaran, Vasudev
A2 - Sijstermans, Frans
A2 - Panchanathan, Sethuraman
T2 - Digital Video Compression: Algorithms and Technologies 1996
Y2 - 31 January 1996 through 2 February 1996
ER -