VLSI Architectures for Multidimensional Transforms

Chaitali Chakrabarti; Joseph JáJá

doi:10.1109/12.83648

VLSI Architectures for Multidimensional Transforms

Chaitali Chakrabarti, Joseph JáJá

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N × N × ••• × N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(N^d+2a), computation time T = O(d N^d/2-a b) and achieve the AT²bound of AT² = 0(n²b²) for constant d, where n = N^dand 0 < a <.

Original language	English (US)
Pages (from-to)	1053-1057
Number of pages	5
Journal	IEEE Transactions on Computers
Volume	40
Issue number	9
DOIs	https://doi.org/10.1109/12.83648
State	Published - Sep 1991

Keywords

AT2 optimal
Area-time treadeoffs
VLSI architecture
multidimensional transforms
rotator unit
subblock transpose unit
sublock rotator

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

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10.1109/12.83648

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@article{027700de6d1041408223ba4f5d1aa356,

title = "VLSI Architectures for Multidimensional Transforms",

abstract = "In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N × N × ••• × N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(Nd+2a), computation time T = O(d Nd/2-a b) and achieve the AT2bound of AT2 = 0(n2b2) for constant d, where n = Ndand 0 < a <.",

keywords = "AT2 optimal, Area-time treadeoffs, VLSI architecture, multidimensional transforms, rotator unit, subblock transpose unit, sublock rotator",

author = "Chaitali Chakrabarti and Joseph J{\'a}J{\'a}",

year = "1991",

month = sep,

doi = "10.1109/12.83648",

language = "English (US)",

volume = "40",

pages = "1053--1057",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "9",

}

TY - JOUR

T1 - VLSI Architectures for Multidimensional Transforms

AU - Chakrabarti, Chaitali

AU - JáJá, Joseph

PY - 1991/9

Y1 - 1991/9

N2 - In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N × N × ••• × N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(Nd+2a), computation time T = O(d Nd/2-a b) and achieve the AT2bound of AT2 = 0(n2b2) for constant d, where n = Ndand 0 < a <.

AB - In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N × N × ••• × N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(Nd+2a), computation time T = O(d Nd/2-a b) and achieve the AT2bound of AT2 = 0(n2b2) for constant d, where n = Ndand 0 < a <.

KW - AT2 optimal

KW - Area-time treadeoffs

KW - VLSI architecture

KW - multidimensional transforms

KW - rotator unit

KW - subblock transpose unit

KW - sublock rotator

UR - http://www.scopus.com/inward/record.url?scp=0004666318&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0004666318&partnerID=8YFLogxK

U2 - 10.1109/12.83648

DO - 10.1109/12.83648

M3 - Article

AN - SCOPUS:0004666318

SN - 0018-9340

VL - 40

SP - 1053

EP - 1057

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 9

ER -

VLSI Architectures for Multidimensional Transforms

Abstract

Keywords

ASJC Scopus subject areas

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