Abstract

In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N × N × ••• × N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(Nd+2a), computation time T = O(d Nd/2-a b) and achieve the AT2bound of AT2 = 0(n2b2) for constant d, where n = Ndand 0 < a <.

Original languageEnglish (US)
Pages (from-to)1053-1057
Number of pages5
JournalIEEE Transactions on Computers
Volume40
Issue number9
DOIs
StatePublished - Sep 1991

Keywords

  • AT<sup>2</sup> optimal
  • Area-time treadeoffs
  • VLSI architecture
  • multidimensional transforms
  • rotator unit
  • subblock transpose unit
  • sublock rotator

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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