Abstract
Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Pages | 215-218 |
| Number of pages | 4 |
| Volume | 4 |
| State | Published - 1994 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |
Other
| Other | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) |
|---|---|
| City | London, England |
| Period | 5/30/94 → 6/2/94 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
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Cite this
Gupta, G., & Chakrabarti, C. (1994). VLSI architectures for hierarchical block matching. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 215-218). IEEE.