VLSI architectures for hierarchical block matching

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages215-218
Number of pages4
Volume4
StatePublished - 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

Other

OtherProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
CityLondon, England
Period5/30/946/2/94

Fingerprint

Data storage equipment
Memory architecture
Motion estimation
Scheduling
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Gupta, G., & Chakrabarti, C. (1994). VLSI architectures for hierarchical block matching. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 215-218). IEEE.

VLSI architectures for hierarchical block matching. / Gupta, Gagan; Chakrabarti, Chaitali.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 1994. p. 215-218.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gupta, G & Chakrabarti, C 1994, VLSI architectures for hierarchical block matching. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 4, IEEE, pp. 215-218, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), London, England, 5/30/94.
Gupta G, Chakrabarti C. VLSI architectures for hierarchical block matching. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4. IEEE. 1994. p. 215-218
Gupta, Gagan ; Chakrabarti, Chaitali. / VLSI architectures for hierarchical block matching. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 1994. pp. 215-218
@inproceedings{b7995dcf6b0b437c8ad4ba4742650a4a,
title = "VLSI architectures for hierarchical block matching",
abstract = "Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.",
author = "Gagan Gupta and Chaitali Chakrabarti",
year = "1994",
language = "English (US)",
volume = "4",
pages = "215--218",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

TY - GEN

T1 - VLSI architectures for hierarchical block matching

AU - Gupta, Gagan

AU - Chakrabarti, Chaitali

PY - 1994

Y1 - 1994

N2 - Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.

AB - Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.

UR - http://www.scopus.com/inward/record.url?scp=0028581750&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028581750&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028581750

VL - 4

SP - 215

EP - 218

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -