VLSI architectures for hierarchical block matching

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages215-218
Number of pages4
Volume4
StatePublished - 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

Other

OtherProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
CityLondon, England
Period5/30/946/2/94

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint Dive into the research topics of 'VLSI architectures for hierarchical block matching'. Together they form a unique fingerprint.

  • Cite this

    Gupta, G., & Chakrabarti, C. (1994). VLSI architectures for hierarchical block matching. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 215-218). IEEE.