VLSI architecture of a scalable matrix transposer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Pages382-391
Number of pages10
DOIs
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA
Duration: Oct 9 1996Oct 11 1996

Other

OtherProceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon
CityAustin, TX, USA
Period10/9/9610/11/96

Fingerprint

very large scale integration
Application specific integrated circuits
Field programmable gate arrays (FPGA)
Signal processing
Image processing
Communication
matrices
application specific integrated circuits
image processing
signal processing
communication

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Fatemi, O., & Panchanathan, S. (1996). VLSI architecture of a scalable matrix transposer. In Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon (pp. 382-391) https://doi.org/10.1109/ICISS.1996.552445

VLSI architecture of a scalable matrix transposer. / Fatemi, O.; Panchanathan, Sethuraman.

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. 1996. p. 382-391.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fatemi, O & Panchanathan, S 1996, VLSI architecture of a scalable matrix transposer. in Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. pp. 382-391, Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon, Austin, TX, USA, 10/9/96. https://doi.org/10.1109/ICISS.1996.552445
Fatemi O, Panchanathan S. VLSI architecture of a scalable matrix transposer. In Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. 1996. p. 382-391 https://doi.org/10.1109/ICISS.1996.552445
Fatemi, O. ; Panchanathan, Sethuraman. / VLSI architecture of a scalable matrix transposer. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. 1996. pp. 382-391
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