VLSI architecture of a scalable matrix transposer

O. Fatemi; S. Panchanathan

doi:10.1109/ICISS.1996.552445

VLSI architecture of a scalable matrix transposer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

Original language	English (US)
Title of host publication	Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Pages	382-391
Number of pages	10
DOIs	https://doi.org/10.1109/ICISS.1996.552445
State	Published - Dec 1 1996
Externally published	Yes
Event	Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA Duration: Oct 9 1996 → Oct 11 1996

Publication series

Name	Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
ISSN (Print)	1063-2204

Other

Other	Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon
City	Austin, TX, USA
Period	10/9/96 → 10/11/96

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering
Hardware and Architecture

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10.1109/ICISS.1996.552445

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Fatemi, O & Panchanathan, S 1996, VLSI architecture of a scalable matrix transposer. in Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon, pp. 382-391, Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon, Austin, TX, USA, 10/9/96. https://doi.org/10.1109/ICISS.1996.552445

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abstract = "In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.",

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BT - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

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VLSI architecture of a scalable matrix transposer

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