VLSI architecture of a scalable matrix transposer

O. Fatemi, S. Panchanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Pages382-391
Number of pages10
DOIs
StatePublished - Dec 1 1996
Externally publishedYes
EventProceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA
Duration: Oct 9 1996Oct 11 1996

Publication series

NameProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
ISSN (Print)1063-2204

Other

OtherProceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon
CityAustin, TX, USA
Period10/9/9610/11/96

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Hardware and Architecture

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    Fatemi, O., & Panchanathan, S. (1996). VLSI architecture of a scalable matrix transposer. In Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon (pp. 382-391). (Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon). https://doi.org/10.1109/ICISS.1996.552445