Abstract
A systolic architecture for computing real-time template matching is presented. The architecture consists of a linear array of P processors, each of which consists of a multiplier-accumulator and shift registers. The architecture achieves optimal speedup with simple data and control flow. The I/O bandwidth problem is handled by storing part of the input image in the shift registers and by circulating the shift registers so that the processor array can compute on the same input multiple times.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | Publ by IEEE |
| Pages | 69-72 |
| Number of pages | 4 |
| Volume | 1 |
| State | Published - 1990 |
| Externally published | Yes |
| Event | 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: May 1 1990 → May 3 1990 |
Other
| Other | 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) |
|---|---|
| City | New Orleans, LA, USA |
| Period | 5/1/90 → 5/3/90 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials