VLSI architecture for template matching

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A systolic architecture for computing real-time template matching is presented. The architecture consists of a linear array of P processors, each of which consists of a multiplier-accumulator and shift registers. The architecture achieves optimal speedup with simple data and control flow. The I/O bandwidth problem is handled by storing part of the input image in the shift registers and by circulating the shift registers so that the processor array can compute on the same input multiple times.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages69-72
Number of pages4
Volume1
StatePublished - 1990
Externally publishedYes
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990

Other

Other1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)
CityNew Orleans, LA, USA
Period5/1/905/3/90

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Chakrabarti, C., & JaJa, J. (1990). VLSI architecture for template matching. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1, pp. 69-72). Publ by IEEE.