VLSI architecture for lifting-based wavelet transform

Kishore Andra, Chaitali Chakrabarti, Tinku Acharya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Scopus citations

Abstract

The Discrete Wavelet Transform (DWT) is the basis for many image compression techniques, such as the upcoming JEPG2000. Lifting-based DWT requires fewer computations compared to the traditional convolution-based approach. In this paper, we propose a VLSI architecture to compute lifting-based 2D DWT, for a set of seven filters recommended in the JPEG2000 verification model. The architecture produces transform coefficients in every clock cycle for three of the filters and in every alternate cycle for the rest of the filters. We also present an efficient memory organization to address the high memory bandwidth requirements. The performance metrics of the proposed architecture have also been furnished.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
PublisherIEEE
Pages70-79
Number of pages10
StatePublished - 2000
Event2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA
Duration: Oct 11 2000Oct 13 2000

Other

Other2000 IEEE Workshop on Signal Processing Systems (SIPS 2000)
CityLafayette, LA, USA
Period10/11/0010/13/00

ASJC Scopus subject areas

  • Engineering(all)

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