VLSI architecture for discrete wavelet transform

A. Grzeszczak, T. H. Yeap, Sethuraman Panchanathan

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.

Original languageEnglish (US)
Pages (from-to)461-464
Number of pages4
JournalUnknown Journal
Volume2
StatePublished - 1994
Externally publishedYes

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Frequency doublers
Wavelet Analysis
Discrete wavelet transforms

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

VLSI architecture for discrete wavelet transform. / Grzeszczak, A.; Yeap, T. H.; Panchanathan, Sethuraman.

In: Unknown Journal, Vol. 2, 1994, p. 461-464.

Research output: Contribution to journalArticle

Grzeszczak, A, Yeap, TH & Panchanathan, S 1994, 'VLSI architecture for discrete wavelet transform', Unknown Journal, vol. 2, pp. 461-464.
Grzeszczak, A. ; Yeap, T. H. ; Panchanathan, Sethuraman. / VLSI architecture for discrete wavelet transform. In: Unknown Journal. 1994 ; Vol. 2. pp. 461-464.
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