VLSI architecture for discrete wavelet transform

A. Grzeszczak; T. H. Yeap; S. Panchanathan

doi:10.1109/ccece.1994.405788

VLSI architecture for discrete wavelet transform

A. Grzeszczak, T. H. Yeap, S. Panchanathan

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.

Original language	English (US)
Pages (from-to)	461-464
Number of pages	4
Journal	Canadian Conference on Electrical and Computer Engineering
Volume	2
DOIs	https://doi.org/10.1109/ccece.1994.405788
State	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 Canadian Conference on Electrical and Computer Engineering. Part 2 (of 2) - Halifax, Can Duration: Sep 25 1994 → Sep 28 1994

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ccece.1994.405788

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title = "VLSI architecture for discrete wavelet transform",

abstract = "This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.",

author = "A. Grzeszczak and Yeap, {T. H.} and S. Panchanathan",

year = "1994",

doi = "10.1109/ccece.1994.405788",

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journal = "Canadian Conference on Electrical and Computer Engineering",

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note = "Proceedings of the 1994 Canadian Conference on Electrical and Computer Engineering. Part 2 (of 2) ; Conference date: 25-09-1994 Through 28-09-1994",

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AU - Grzeszczak, A.

AU - Yeap, T. H.

AU - Panchanathan, S.

PY - 1994

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N2 - This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.

AB - This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.

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U2 - 10.1109/ccece.1994.405788

DO - 10.1109/ccece.1994.405788

M3 - Conference article

AN - SCOPUS:0028721455

SN - 0840-7789

VL - 2

SP - 461

EP - 464

JO - Canadian Conference on Electrical and Computer Engineering

JF - Canadian Conference on Electrical and Computer Engineering

T2 - Proceedings of the 1994 Canadian Conference on Electrical and Computer Engineering. Part 2 (of 2)

Y2 - 25 September 1994 through 28 September 1994

ER -

VLSI architecture for discrete wavelet transform

Abstract

ASJC Scopus subject areas

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