VLSI architecture for DFT

Eric Chan; Sethuraman Panchanathan

VLSI architecture for DFT

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.

Original language	English (US)
Title of host publication	Midwest Symposium on Circuits and Systems
Publisher	Publ by IEEE
Pages	292-295
Number of pages	4
ISBN (Print)	0780317610
State	Published - Dec 1 1993
Externally published	Yes
Event	Proceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA Duration: Aug 16 1993 → Aug 18 1993

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	1

Other

Other	Proceedings of the 36th Midwest Symposium on Circuits and Systems
City	Detroit, MI, USA
Period	8/16/93 → 8/18/93

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "VLSI architecture for DFT",

abstract = "In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.",

author = "Eric Chan and Sethuraman Panchanathan",

year = "1993",

month = dec,

day = "1",

language = "English (US)",

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series = "Midwest Symposium on Circuits and Systems",

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note = "Proceedings of the 36th Midwest Symposium on Circuits and Systems ; Conference date: 16-08-1993 Through 18-08-1993",

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AU - Panchanathan, Sethuraman

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N2 - In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.

AB - In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.

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M3 - Conference contribution

AN - SCOPUS:0027755592

SN - 0780317610

T3 - Midwest Symposium on Circuits and Systems

SP - 292

EP - 295

BT - Midwest Symposium on Circuits and Systems

PB - Publ by IEEE

T2 - Proceedings of the 36th Midwest Symposium on Circuits and Systems

Y2 - 16 August 1993 through 18 August 1993

ER -

VLSI architecture for DFT

Abstract

Publication series

Other

ASJC Scopus subject areas

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Cite this