Vertical p-channel double-gate MOSFETs

J. Moers, S. Trellenkamp, Avd Hart, M. Goryll, S. Mantl, P. Kordos, H. Luth

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 μS/μm, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.

Original languageEnglish (US)
Title of host publicationESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
EditorsJose Franca, Paulo Freitas
PublisherIEEE Computer Society
Pages143-146
Number of pages4
ISBN (Electronic)0780379993
ISBN (Print)9780780379992
DOIs
StatePublished - Jan 1 2003
Externally publishedYes
Event33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal
Duration: Sep 16 2003Sep 18 2003

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other33rd European Solid-State Device Research Conference, ESSDERC 2003
CountryPortugal
CityEstoril
Period9/16/039/18/03

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Moers, J., Trellenkamp, S., Hart, A., Goryll, M., Mantl, S., Kordos, P., & Luth, H. (2003). Vertical p-channel double-gate MOSFETs. In J. Franca, & P. Freitas (Eds.), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference (pp. 143-146). [1256831] (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2003.1256831