Vertical p-channel double-gate MOSFETs

J. Moers; S. Trellenkamp; Avd Hart; M. Goryll; S. Mantl; P. Kordos; H. Luth

doi:10.1109/ESSDERC.2003.1256831

Vertical p-channel double-gate MOSFETs

J. Moers, S. Trellenkamp, Avd Hart, M. Goryll, S. Mantl, P. Kordos, H. Luth

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 μS/μm, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.

Original language	English (US)
Title of host publication	ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
Editors	Jose Franca, Paulo Freitas
Publisher	IEEE Computer Society
Pages	143-146
Number of pages	4
ISBN (Electronic)	0780379993
ISBN (Print)	9780780379992
DOIs	https://doi.org/10.1109/ESSDERC.2003.1256831
State	Published - 2003
Externally published	Yes
Event	33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal Duration: Sep 16 2003 → Sep 18 2003

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Other

Other	33rd European Solid-State Device Research Conference, ESSDERC 2003
Country/Territory	Portugal
City	Estoril
Period	9/16/03 → 9/18/03

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ESSDERC.2003.1256831

Cite this

Moers, J., Trellenkamp, S., Hart, A., Goryll, M., Mantl, S., Kordos, P., & Luth, H. (2003). Vertical p-channel double-gate MOSFETs. In J. Franca, & P. Freitas (Eds.), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference (pp. 143-146). Article 1256831 (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2003.1256831

Vertical p-channel double-gate MOSFETs. / Moers, J.; Trellenkamp, S.; Hart, Avd et al.
ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference. ed. / Jose Franca; Paulo Freitas. IEEE Computer Society, 2003. p. 143-146 1256831 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Moers, J, Trellenkamp, S, Hart, A, Goryll, M, Mantl, S, Kordos, P & Luth, H 2003, Vertical p-channel double-gate MOSFETs. in J Franca & P Freitas (eds), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference., 1256831, European Solid-State Device Research Conference, IEEE Computer Society, pp. 143-146, 33rd European Solid-State Device Research Conference, ESSDERC 2003, Estoril, Portugal, 9/16/03. https://doi.org/10.1109/ESSDERC.2003.1256831

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AB - Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 μS/μm, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.

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Vertical p-channel double-gate MOSFETs

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