Versa: A 36-Core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory

Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan Yu Chen; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong; Trevor Mudge; Chaitali Chakrabarti; David Blaauw; Ronald Dreslinski; Hun Seok Kim

doi:10.1109/JSSC.2022.3140241

Versa: A 36-Core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory

Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor Mudge, Chaitali Chakrabarti, David Blaauw, Ronald Dreslinski, Hun Seok Kim

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 times improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa's design features culminate in median energy-efficiency improvements of 37.2 times and 11.6 times over mobile CPU and GPU baselines, respectively.

Original language	English (US)
Pages (from-to)	986-998
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	57
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2022.3140241
State	Published - Apr 1 2022
Externally published	Yes

Keywords

Accelerators
data movement
data reuse
energy efficiency
interconnect
multicore architecture
on-chip memory
programmability
reconfiguration
systolic arrays

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2022.3140241

Cite this

@article{4e133d5ec0684508ab795cdc2b1443ad,

title = "Versa: A 36-Core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory",

abstract = "We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 times improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa's design features culminate in median energy-efficiency improvements of 37.2 times and 11.6 times over mobile CPU and GPU baselines, respectively.",

keywords = "Accelerators, data movement, data reuse, energy efficiency, interconnect, multicore architecture, on-chip memory, programmability, reconfiguration, systolic arrays",

author = "Sung Kim and Morteza Fayazi and Alhad Daftardar and Chen, {Kuan Yu} and Jielun Tan and Subhankar Pal and Tutu Ajayi and Yan Xiong and Trevor Mudge and Chaitali Chakrabarti and David Blaauw and Ronald Dreslinski and Kim, {Hun Seok}",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2022",

month = apr,

day = "1",

doi = "10.1109/JSSC.2022.3140241",

language = "English (US)",

volume = "57",

pages = "986--998",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Versa

T2 - A 36-Core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory

AU - Kim, Sung

AU - Fayazi, Morteza

AU - Daftardar, Alhad

AU - Chen, Kuan Yu

AU - Tan, Jielun

AU - Pal, Subhankar

AU - Ajayi, Tutu

AU - Xiong, Yan

AU - Mudge, Trevor

AU - Chakrabarti, Chaitali

AU - Blaauw, David

AU - Dreslinski, Ronald

AU - Kim, Hun Seok

PY - 2022/4/1

Y1 - 2022/4/1

N2 - We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 times improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa's design features culminate in median energy-efficiency improvements of 37.2 times and 11.6 times over mobile CPU and GPU baselines, respectively.

AB - We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 times improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa's design features culminate in median energy-efficiency improvements of 37.2 times and 11.6 times over mobile CPU and GPU baselines, respectively.

KW - Accelerators

KW - data movement

KW - data reuse

KW - energy efficiency

KW - interconnect

KW - multicore architecture

KW - on-chip memory

KW - programmability

KW - reconfiguration

KW - systolic arrays

UR - http://www.scopus.com/inward/record.url?scp=85124207207&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85124207207&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2022.3140241

DO - 10.1109/JSSC.2022.3140241

M3 - Article

AN - SCOPUS:85124207207

SN - 0018-9200

VL - 57

SP - 986

EP - 998

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -

Versa: A 36-Core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this