Verilog-A compact model for oxide-based resistive random access memory (RRAM)

Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse H. Engel, Ximeng Guan, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations

Abstract

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.

Original languageEnglish (US)
Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41-44
Number of pages4
ISBN (Electronic)9781479952885
DOIs
StatePublished - Oct 20 2014
Event2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, Japan
Duration: Sep 9 2014Sep 11 2014

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Other

Other2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
CountryJapan
CityYokohama
Period9/9/149/11/14

Keywords

  • Compact model
  • RRAM
  • Verilog-A
  • variations

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

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    Jiang, Z., Yu, S., Wu, Y., Engel, J. H., Guan, X., & Wong, H. S. P. (2014). Verilog-A compact model for oxide-based resistive random access memory (RRAM). In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (pp. 41-44). [6931558] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2014.6931558