Verilog-A compact model for oxide-based resistive random access memory (RRAM)

Zizhen Jiang; Shimeng Yu; Yi Wu; Jesse H. Engel; Ximeng Guan; H. S Philip Wong

doi:10.1109/SISPAD.2014.6931558

Verilog-A compact model for oxide-based resistive random access memory (RRAM)

Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse H. Engel, Ximeng Guan, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

115 Scopus citations

Abstract

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.

Original language	English (US)
Title of host publication	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	41-44
Number of pages	4
ISBN (Electronic)	9781479952885
DOIs	https://doi.org/10.1109/SISPAD.2014.6931558
State	Published - Oct 20 2014
Event	2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, Japan Duration: Sep 9 2014 → Sep 11 2014

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Other

Other	2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
Country/Territory	Japan
City	Yokohama
Period	9/9/14 → 9/11/14

Keywords

Compact model
RRAM
Verilog-A
variations

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Modeling and Simulation

Access to Document

10.1109/SISPAD.2014.6931558

Cite this

Jiang, Z., Yu, S., Wu, Y., Engel, J. H., Guan, X., & Wong, H. S. P. (2014). Verilog-A compact model for oxide-based resistive random access memory (RRAM). In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (pp. 41-44). Article 6931558 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2014.6931558

Verilog-A compact model for oxide-based resistive random access memory (RRAM). / Jiang, Zizhen; Yu, Shimeng; Wu, Yi et al.
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc., 2014. p. 41-44 6931558 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jiang, Z, Yu, S, Wu, Y, Engel, JH, Guan, X & Wong, HSP 2014, Verilog-A compact model for oxide-based resistive random access memory (RRAM). in International Conference on Simulation of Semiconductor Processes and Devices, SISPAD., 6931558, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, Institute of Electrical and Electronics Engineers Inc., pp. 41-44, 2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014, Yokohama, Japan, 9/9/14. https://doi.org/10.1109/SISPAD.2014.6931558

Jiang Z, Yu S, Wu Y, Engel JH, Guan X, Wong HSP. Verilog-A compact model for oxide-based resistive random access memory (RRAM). In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc. 2014. p. 41-44. 6931558. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2014.6931558

Jiang, Zizhen ; Yu, Shimeng ; Wu, Yi et al. / Verilog-A compact model for oxide-based resistive random access memory (RRAM). International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 41-44 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

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Verilog-A compact model for oxide-based resistive random access memory (RRAM)

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Keywords

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