Abstract
In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form delay metrics to compute interconnect delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of delay of 1% and 4% on average, respectively.
Original language | English (US) |
---|---|
Title of host publication | Proceedings - Design Automation Conference |
Pages | 381-384 |
Number of pages | 4 |
State | Published - 2004 |
Event | Proceedings of the 41st Design Automation Conference - San Diego, CA, United States Duration: Jun 7 2004 → Jun 11 2004 |
Other
Other | Proceedings of the 41st Design Automation Conference |
---|---|
Country/Territory | United States |
City | San Diego, CA |
Period | 6/7/04 → 6/11/04 |
Keywords
- Design
- Performance
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering