Variational delay metrics for interconnect timing analysis

Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani Nassif, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

70 Scopus citations

Abstract

In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form delay metrics to compute interconnect delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of delay of 1% and 4% on average, respectively.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages381-384
Number of pages4
StatePublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Other

OtherProceedings of the 41st Design Automation Conference
CountryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Keywords

  • Design
  • Performance

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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  • Cite this

    Agarwal, K., Sylvester, D., Blaauw, D., Liu, F., Nassif, S., & Vrudhula, S. (2004). Variational delay metrics for interconnect timing analysis. In Proceedings - Design Automation Conference (pp. 381-384)