TY - JOUR
T1 - Variability induced by line edge roughness in double-gate dopant-segregated schottky MOSFETs
AU - Yang, Yunxiang
AU - Yu, Shimeng
AU - Zeng, Lang
AU - Du, Gang
AU - Kang, Jinfeng
AU - Zhao, Yuning
AU - Han, Ruqi
AU - Liu, Xiaoyan
N1 - Funding Information:
Manuscript received June 11, 2009; revised October 26, 2009; accepted November 5, 2009. Date of publication December 15, 2009; date of current version March 9, 2011. This work is supported by the Grant NKBRP2006CB302705 and by the National Natural Science Foundation of China under Grant 60736030. The review of this paper was arranged by Associate Editor K. Matsumoto.
PY - 2011/3
Y1 - 2011/3
N2 - Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.
AB - Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.
KW - Dopant-segregated Schottky MOSFETs (DSS-MOSFETs)
KW - Schottky barrier (SB)
KW - line edge roughness (LER)
KW - technology computer-aided design (TCAD) simulation
KW - variations
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U2 - 10.1109/TNANO.2009.2037222
DO - 10.1109/TNANO.2009.2037222
M3 - Article
AN - SCOPUS:79952687807
SN - 1536-125X
VL - 10
SP - 244
EP - 249
JO - IEEE Transactions on Nanotechnology
JF - IEEE Transactions on Nanotechnology
IS - 2
M1 - 5353696
ER -