TY - GEN
T1 - Using TMR to mitigate SEUs for digital instrumentation and control in nuclear power plants
AU - Wang, Xin
AU - Holbert, Keith
AU - Clark, Lawrence T.
PY - 2010
Y1 - 2010
N2 - In this paper, methodologies to perform triple modular redundancy (TMR) insertion to reduce single event upsets (SEUs) in digital instrumentation and control (I&C) in nuclear power plants (NPPs) are presented. Field programmable gate arrays (FPGAs) are being increasingly used for digital I&C in NPPs to perform various tasks, including plant control, monitoring and protection because of low cost, re-configurability and low design turn-around time. But the memory and logic in FPGAs are susceptible to SEUs. TMR has become a common SEU mitigation design technique. However, TMR introduces significant overhead because of its full hardware redundancy. For NPPs, the overheads are insignificant, especially compared to reliability requirements. Formulae derived in this paper indicate that the bound, i.e., the maximal probability, of two simultaneous errors [PE]max is inversely proportional to the number of logic partitions in a TMR design, when each redundant logic block in every logic partition has the same number of sensitive nodes. Although the maximum logic partitioning design cannot completely eliminate the possibility of two simultaneous upsets, for the example test circuit it is found that [P E]max is reduced dramatically from 66.67% for minimum logic partitioning to 4.44% for maximum logic partitioning. Results show that the overheads of the maximum logic partitioning TMR design are acceptable compared to its high reliability.
AB - In this paper, methodologies to perform triple modular redundancy (TMR) insertion to reduce single event upsets (SEUs) in digital instrumentation and control (I&C) in nuclear power plants (NPPs) are presented. Field programmable gate arrays (FPGAs) are being increasingly used for digital I&C in NPPs to perform various tasks, including plant control, monitoring and protection because of low cost, re-configurability and low design turn-around time. But the memory and logic in FPGAs are susceptible to SEUs. TMR has become a common SEU mitigation design technique. However, TMR introduces significant overhead because of its full hardware redundancy. For NPPs, the overheads are insignificant, especially compared to reliability requirements. Formulae derived in this paper indicate that the bound, i.e., the maximal probability, of two simultaneous errors [PE]max is inversely proportional to the number of logic partitions in a TMR design, when each redundant logic block in every logic partition has the same number of sensitive nodes. Although the maximum logic partitioning design cannot completely eliminate the possibility of two simultaneous upsets, for the example test circuit it is found that [P E]max is reduced dramatically from 66.67% for minimum logic partitioning to 4.44% for maximum logic partitioning. Results show that the overheads of the maximum logic partitioning TMR design are acceptable compared to its high reliability.
KW - Field programmable gate arrays (FPGAs)
KW - Instrumentation and control (I&C)
KW - Logic partitioning
KW - Single event upset (SEU)
KW - Triple modular redundancy (TMR)
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M3 - Conference contribution
AN - SCOPUS:79958271788
SN - 9781617822667
T3 - 7th International Topical Meeting on Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies 2010, NPIC and HMIT 2010
SP - 925
EP - 934
BT - 7th International Topical Meeting on Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies 2010, NPIC and HMIT 2010
T2 - 7th International Topical Meeting on Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies 2010, NPIC and HMIT 2010
Y2 - 7 November 2010 through 11 November 2010
ER -