UnSync: A soft error resilient redundant multicore architecture

Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
Pages632-641
Number of pages10
DOIs
StatePublished - 2011
Event40th International Conference on Parallel Processing, ICPP 2011 - Taipei City, Taiwan, Province of China
Duration: Sep 13 2011Sep 16 2011

Other

Other40th International Conference on Parallel Processing, ICPP 2011
CountryTaiwan, Province of China
CityTaipei City
Period9/13/119/16/11

Fingerprint

Soft Error
Hardware
Chip multiprocessors
Redundancy
Transistors
Electric power utilization
Multiprocessor Systems
Resilience
Availability
Vulnerability
Recovery
Power Consumption
Architecture
Timing
Charge
Industry
Synthesis
Benchmark
Cycle
Resources

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Jeyapaul, R., Hong, F., Rhisheekesan, A., Shrivastava, A., & Lee, K. (2011). UnSync: A soft error resilient redundant multicore architecture. In Proceedings of the International Conference on Parallel Processing (pp. 632-641). [6047231] https://doi.org/10.1109/ICPP.2011.76

UnSync : A soft error resilient redundant multicore architecture. / Jeyapaul, Reiley; Hong, Fei; Rhisheekesan, Abhishek; Shrivastava, Aviral; Lee, Kyoungwoo.

Proceedings of the International Conference on Parallel Processing. 2011. p. 632-641 6047231.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jeyapaul, R, Hong, F, Rhisheekesan, A, Shrivastava, A & Lee, K 2011, UnSync: A soft error resilient redundant multicore architecture. in Proceedings of the International Conference on Parallel Processing., 6047231, pp. 632-641, 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, Taiwan, Province of China, 9/13/11. https://doi.org/10.1109/ICPP.2011.76
Jeyapaul R, Hong F, Rhisheekesan A, Shrivastava A, Lee K. UnSync: A soft error resilient redundant multicore architecture. In Proceedings of the International Conference on Parallel Processing. 2011. p. 632-641. 6047231 https://doi.org/10.1109/ICPP.2011.76
Jeyapaul, Reiley ; Hong, Fei ; Rhisheekesan, Abhishek ; Shrivastava, Aviral ; Lee, Kyoungwoo. / UnSync : A soft error resilient redundant multicore architecture. Proceedings of the International Conference on Parallel Processing. 2011. pp. 632-641
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