Unitary Shift-Register Realizations of Sequential Machines

C. C. Su, S. S. Yau

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.

Original languageEnglish (US)
Pages (from-to)312-324
Number of pages13
JournalIEEE Transactions on Computers
VolumeC-17
Issue number4
DOIs
StatePublished - Apr 1968
Externally publishedYes

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Keywords

  • Algorithms many-to-one state assignments sequential machines shift-register realizations unitary coding

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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