### Abstract

The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.

Original language | English (US) |
---|---|

Pages (from-to) | 312-324 |

Number of pages | 13 |

Journal | IEEE Transactions on Computers |

Volume | C-17 |

Issue number | 4 |

DOIs | |

State | Published - 1968 |

Externally published | Yes |

### Fingerprint

### Keywords

- Algorithms many-to-one state assignments sequential machines shift-register realizations unitary coding

### ASJC Scopus subject areas

- Computational Theory and Mathematics
- Hardware and Architecture
- Software
- Theoretical Computer Science

### Cite this

*IEEE Transactions on Computers*,

*C-17*(4), 312-324. https://doi.org/10.1109/TC.1968.229383

**Unitary Shift-Register Realizations of Sequential Machines.** / Su, C. C.; Yau, Sik-Sang.

Research output: Contribution to journal › Article

*IEEE Transactions on Computers*, vol. C-17, no. 4, pp. 312-324. https://doi.org/10.1109/TC.1968.229383

}

TY - JOUR

T1 - Unitary Shift-Register Realizations of Sequential Machines

AU - Su, C. C.

AU - Yau, Sik-Sang

PY - 1968

Y1 - 1968

N2 - The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.

AB - The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.

KW - Algorithms many-to-one state assignments sequential machines shift-register realizations unitary coding

UR - http://www.scopus.com/inward/record.url?scp=84911307320&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84911307320&partnerID=8YFLogxK

U2 - 10.1109/TC.1968.229383

DO - 10.1109/TC.1968.229383

M3 - Article

AN - SCOPUS:84911307320

VL - C-17

SP - 312

EP - 324

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 4

ER -