Ultra-low-voltage robust design issues in deep-submicron CMOS

Andrei Vladimirescu, Yu Cao, Olivier Thomas, Huifang Qin, Dejan Markovic, Alexandre Valentian, Razvan Ionita, Jan Rabaey, Amara Amara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Design challenges for operating CMOS circuits fabricated in 0.13μm and finer technologies at ultra-low-voltages are analyzed. The design goal consists in minimizing energy by reducing V DD while maintaining delay and yield at acceptable levels in the presence of increasing variability of process parameters. First, an estimation model developed to accurately predict operation of bulk-and SOI-CMOS in subthreshold is described. The relation between yield, energy, delay and device parameter distributions is examined next along with tradeoffs necessary to achieve the desired performance point. The main objective of minimizing energy is explored for SRAM cells by predicting the minimum V DD based on the data-retention voltage, DRV, and, acceptable signal-to-noise margins, SNM. Experimental data from a 4kB-SRAM test chip in 0.13μm CMOS are presented demonstrating a 90% leakage reduction potential in standby under reduced bias of 250mV.

Original languageEnglish (US)
Title of host publicationConference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004
Pages49-52
Number of pages4
StatePublished - Dec 1 2004
Externally publishedYes
EventConference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004 - Montreal, Que., Canada
Duration: Jun 20 2004Jun 23 2004

Publication series

NameConference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Other

OtherConference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004
CountryCanada
CityMontreal, Que.
Period6/20/046/23/04

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Vladimirescu, A., Cao, Y., Thomas, O., Qin, H., Markovic, D., Valentian, A., Ionita, R., Rabaey, J., & Amara, A. (2004). Ultra-low-voltage robust design issues in deep-submicron CMOS. In Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004 (pp. 49-52). (Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004).