Ultra-low power radiation hardened by design memory circuits

Tai Hua Chen, Jinhui Chen, Lawrence T. Clark, Jonathan E. Knudsen, Giby Samson

Research output: Contribution to journalArticle

15 Scopus citations

Abstract

A 32 × 18 bit ultra-low power radiation-hardened by design (RHBD) register file is fabricated on a 130-nm bulk CMOS technology. Register file readout circuitry allows functionality down to V DD = 206 mV. Dual interlocked cell (DICE) storage provides SEU immunity above V DD = 450 mV in accelerated heavy ion testing. This memory is compared to a larger one using identical ultra low voltage circuit design techniques, but un-hardened, i.e., with conventional latch storage and using only two-edge transistor layout and no guard rings. The un-hardened ultra low voltage memory exhibits 100 × lower leakage post-irradiation to 500 krad(Si), when irradiated and measured at V DD = 500 mV, than when irradiated and measured with V DD = 1.2 V. Hence, for ultra-low power, ultra-low V DD circuits, TID hardening techniques may be unnecessary. Read energy dissipated by the RHBD memory is 10.3 f J per bit per operation when operated at 320 mV. The maximum operating frequency is 5 MHz at the same supply voltage.

Original languageEnglish (US)
Pages (from-to)2004-2011
Number of pages8
JournalIEEE Transactions on Nuclear Science
Volume54
Issue number6
DOIs
StatePublished - Dec 1 2007

    Fingerprint

Keywords

  • Dual interlocked cell (DICE)
  • Radiation hardening
  • Register file
  • Subthreshold circuits
  • Ultra-low power

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

Cite this

Chen, T. H., Chen, J., Clark, L. T., Knudsen, J. E., & Samson, G. (2007). Ultra-low power radiation hardened by design memory circuits. IEEE Transactions on Nuclear Science, 54(6), 2004-2011. https://doi.org/10.1109/TNS.2007.909909