A new memory bus concept that has the potential to dramatically improve double data rate (DDR) memory speed is presented. The memory signal is modulated onto an RF carrier which is routed using substrate integrated waveguide (SIW) interconnect technology. The channel is divided into multi-carrier bands where each symbol is modulated onto one carrier using 64-QAM format. The conventional DDR bus is entirely mapped into the proposed multi-carrier memory channel architecture (MCMCA). At the receiver the signal is demodulated and then delivered to SDRAM devices. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 30 Gbps data transfer with error vector magnitude (EVM) not exceeding 2.26% and phase error of 1.07 degree or less.