Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness

Shimeng Yu, Yuning Zhao, Gang Du, Jinfeng Kang, Ruqi Han, Xiaoyan Liu

Research output: Contribution to journalArticle

Abstract

Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (Tsi) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing T si can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length.

Original languageEnglish (US)
Article number04C052
JournalJapanese Journal of Applied Physics
Volume48
Issue number4 PART 2
DOIs
StatePublished - Apr 1 2009

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Fingerprint Dive into the research topics of 'Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness'. Together they form a unique fingerprint.

  • Cite this