Abstract
Range-Doppler Algorithm (RDA) and Chirp Scaling Algorithm (CSA) are two widely used Synthetic Aperture Radar (SAR) imaging schemes. Both require multiple transpose operations which increase the total processing time significantly. In this paper, we propose transpose-free flow for both RDA and CSA. This is achieved by modifying the existing flows in order to utilize the access patterns favored by the external memory. As a result, the peak performance of the memory is sustained and the processing time shortened. The proposed Field Programmable Gate Array (FPGA)-based implementation outperforms the existing SAR accelerators; it computes RDA and CSA on data size of 4, 096 × 4, 096 in 323ms and 162ms, respectively.
Original language | English (US) |
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Title of host publication | ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems |
Pages | 762-765 |
Number of pages | 4 |
DOIs | |
State | Published - 2012 |
Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012 |
Other
Other | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 5/20/12 → 5/23/12 |
Keywords
- DRAM
- FFT
- FPGA
- SAR
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering