Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Hong Yu Chen; Bin Gao; Haitong Li; Rui Liu; Peng Huang; Zhe Chen; Bing Chen; Feifei Zhang; Liang Zhao; Zizhen Jiang; Lifeng Liu; Xiaoyan Liu; Jinfeng Kang; Shimeng Yu; Yoshio Nishi; H. S Philip Wong

doi:10.1109/VLSIT.2014.6894434

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Hong Yu Chen, Bin Gao, Haitong Li, Rui Liu, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Zizhen Jiang, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang, Shimeng Yu, Yoshio Nishi, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

Original language	English (US)
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479933310
DOIs	https://doi.org/10.1109/VLSIT.2014.6894434
State	Published - Sep 8 2014
Event	34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States Duration: Jun 9 2014 → Jun 12 2014

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	34th Symposium on VLSI Technology, VLSIT 2014
Country/Territory	United States
City	Honolulu
Period	6/9/14 → 6/12/14

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2014.6894434

Cite this

Chen, H. Y., Gao, B., Li, H., Liu, R., Huang, P., Chen, Z., Chen, B., Zhang, F., Zhao, L., Jiang, Z., Liu, L., Liu, X., Kang, J., Yu, S., Nishi, Y., & Wong, H. S. P. (2014). Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays. In Digest of Technical Papers - Symposium on VLSI Technology Article 6894434 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2014.6894434

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays. / Chen, Hong Yu; Gao, Bin; Li, Haitong et al.
Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 2014. 6894434 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, HY, Gao, B, Li, H, Liu, R, Huang, P, Chen, Z, Chen, B, Zhang, F, Zhao, L, Jiang, Z, Liu, L, Liu, X, Kang, J, Yu, S, Nishi, Y & Wong, HSP 2014, Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays. in Digest of Technical Papers - Symposium on VLSI Technology., 6894434, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 34th Symposium on VLSI Technology, VLSIT 2014, Honolulu, United States, 6/9/14. https://doi.org/10.1109/VLSIT.2014.6894434

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abstract = "3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.",

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Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

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