Tolerating hard faults in microprocessor array structures

Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

65 Citations (Scopus)

Abstract

In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row." We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Dependable Systems and Networks
Pages51-60
Number of pages10
StatePublished - 2004
Externally publishedYes
Event2004 International Conference on Dependable Systems and Networks - Florence, Italy
Duration: Jun 28 2004Jul 1 2004

Other

Other2004 International Conference on Dependable Systems and Networks
CountryItaly
CityFlorence
Period6/28/047/1/04

Fingerprint

Microprocessor chips
Masks
Hardware
Recovery

ASJC Scopus subject areas

  • Computer Science (miscellaneous)
  • Computer Networks and Communications

Cite this

Bower, F. A., Shealy, P. G., Ozev, S., & Sorin, D. J. (2004). Tolerating hard faults in microprocessor array structures. In Proceedings of the International Conference on Dependable Systems and Networks (pp. 51-60)

Tolerating hard faults in microprocessor array structures. / Bower, Fred A.; Shealy, Paul G.; Ozev, Sule; Sorin, Daniel J.

Proceedings of the International Conference on Dependable Systems and Networks. 2004. p. 51-60.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bower, FA, Shealy, PG, Ozev, S & Sorin, DJ 2004, Tolerating hard faults in microprocessor array structures. in Proceedings of the International Conference on Dependable Systems and Networks. pp. 51-60, 2004 International Conference on Dependable Systems and Networks, Florence, Italy, 6/28/04.
Bower FA, Shealy PG, Ozev S, Sorin DJ. Tolerating hard faults in microprocessor array structures. In Proceedings of the International Conference on Dependable Systems and Networks. 2004. p. 51-60
Bower, Fred A. ; Shealy, Paul G. ; Ozev, Sule ; Sorin, Daniel J. / Tolerating hard faults in microprocessor array structures. Proceedings of the International Conference on Dependable Systems and Networks. 2004. pp. 51-60
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