Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks

Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-sun Seo, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

258 Scopus citations

Abstract

Convolutional Neural Networks (CNNs) have gained popularity in many computer vision applications such as image classification, face detection, and video analysis, because of their ability to train and classify with high accuracy. Due to multiple convolution and fully-connected layers that are compute- /memory-intensive, it is difficult to perform real-time classification with low power consumption on today's computing systems. FPGAS have been widely explored as hardware accelerators for CNNs because of their reconfigurability and energy efficiency, as well as fast turn-around-time, especially with high-level synthesis methodologies. Previous FPGA-based CNN accelerators, however, typically implemented generic accelerators agnostic to the CNN configuration, where the reconfigurable capabilities of FPGAS are not fully leveraged to maximize the overall system throughput. In this work, we present a systematic design space exploration methodology to maximize the throughput of an OpenCL-based FPGA accelerator for a given CNN model, considering the FPGA resource constraints such as on-chip memory, registers, computational resources and external memory bandwidth. The proposed methodology is demonstrated by optimizing two representative large-scale CNNs, AlexNet and VGG, on two Altera Stratix-V FPGA platforms, DE5-Net and P395-D8 boards, which have different hardware resources. We achieve a peak performance of 136.5 GOPS for convolution operation, and 117.8 GOPS for the entire VGG network that performs ImageNet classification on P395-D8 board.

Original languageEnglish (US)
Title of host publicationFPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
PublisherAssociation for Computing Machinery, Inc
Pages16-25
Number of pages10
ISBN (Print)9781450338561
DOIs
StatePublished - Feb 21 2016
Event2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016 - Monterey, United States
Duration: Feb 21 2016Feb 23 2016

Other

Other2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016
CountryUnited States
CityMonterey
Period2/21/162/23/16

Keywords

  • Convolutional neural networks
  • FPGA
  • OpenCL
  • Optimization

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Suda, N., Chandra, V., Dasika, G., Mohanty, A., Ma, Y., Vrudhula, S., Seo, J., & Cao, Y. (2016). Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks. In FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 16-25). Association for Computing Machinery, Inc. https://doi.org/10.1145/2847263.2847276