Abstract
Convolutional Neural Networks (CNNs) have gained popularity in many computer vision applications such as image classification, face detection, and video analysis, because of their ability to train and classify with high accuracy. Due to multiple convolution and fully-connected layers that are compute- /memory-intensive, it is difficult to perform real-time classification with low power consumption on today's computing systems. FPGAS have been widely explored as hardware accelerators for CNNs because of their reconfigurability and energy efficiency, as well as fast turn-around-time, especially with high-level synthesis methodologies. Previous FPGA-based CNN accelerators, however, typically implemented generic accelerators agnostic to the CNN configuration, where the reconfigurable capabilities of FPGAS are not fully leveraged to maximize the overall system throughput. In this work, we present a systematic design space exploration methodology to maximize the throughput of an OpenCL-based FPGA accelerator for a given CNN model, considering the FPGA resource constraints such as on-chip memory, registers, computational resources and external memory bandwidth. The proposed methodology is demonstrated by optimizing two representative large-scale CNNs, AlexNet and VGG, on two Altera Stratix-V FPGA platforms, DE5-Net and P395-D8 boards, which have different hardware resources. We achieve a peak performance of 136.5 GOPS for convolution operation, and 117.8 GOPS for the entire VGG network that performs ImageNet classification on P395-D8 board.
| Original language | English (US) |
|---|---|
| Title of host publication | FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays |
| Publisher | Association for Computing Machinery, Inc |
| Pages | 16-25 |
| Number of pages | 10 |
| ISBN (Print) | 9781450338561 |
| DOIs | |
| State | Published - Feb 21 2016 |
| Event | 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016 - Monterey, United States Duration: Feb 21 2016 → Feb 23 2016 |
Other
| Other | 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016 |
|---|---|
| Country | United States |
| City | Monterey |
| Period | 2/21/16 → 2/23/16 |
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Keywords
- Convolutional neural networks
- FPGA
- OpenCL
- Optimization
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks. / Suda, Naveen; Chandra, Vikas; Dasika, Ganesh; Mohanty, Abinash; Ma, Yufei; Vrudhula, Sarma; Seo, Jae-sun; Cao, Yu.
FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery, Inc, 2016. p. 16-25.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks
AU - Suda, Naveen
AU - Chandra, Vikas
AU - Dasika, Ganesh
AU - Mohanty, Abinash
AU - Ma, Yufei
AU - Vrudhula, Sarma
AU - Seo, Jae-sun
AU - Cao, Yu
PY - 2016/2/21
Y1 - 2016/2/21
N2 - Convolutional Neural Networks (CNNs) have gained popularity in many computer vision applications such as image classification, face detection, and video analysis, because of their ability to train and classify with high accuracy. Due to multiple convolution and fully-connected layers that are compute- /memory-intensive, it is difficult to perform real-time classification with low power consumption on today's computing systems. FPGAS have been widely explored as hardware accelerators for CNNs because of their reconfigurability and energy efficiency, as well as fast turn-around-time, especially with high-level synthesis methodologies. Previous FPGA-based CNN accelerators, however, typically implemented generic accelerators agnostic to the CNN configuration, where the reconfigurable capabilities of FPGAS are not fully leveraged to maximize the overall system throughput. In this work, we present a systematic design space exploration methodology to maximize the throughput of an OpenCL-based FPGA accelerator for a given CNN model, considering the FPGA resource constraints such as on-chip memory, registers, computational resources and external memory bandwidth. The proposed methodology is demonstrated by optimizing two representative large-scale CNNs, AlexNet and VGG, on two Altera Stratix-V FPGA platforms, DE5-Net and P395-D8 boards, which have different hardware resources. We achieve a peak performance of 136.5 GOPS for convolution operation, and 117.8 GOPS for the entire VGG network that performs ImageNet classification on P395-D8 board.
AB - Convolutional Neural Networks (CNNs) have gained popularity in many computer vision applications such as image classification, face detection, and video analysis, because of their ability to train and classify with high accuracy. Due to multiple convolution and fully-connected layers that are compute- /memory-intensive, it is difficult to perform real-time classification with low power consumption on today's computing systems. FPGAS have been widely explored as hardware accelerators for CNNs because of their reconfigurability and energy efficiency, as well as fast turn-around-time, especially with high-level synthesis methodologies. Previous FPGA-based CNN accelerators, however, typically implemented generic accelerators agnostic to the CNN configuration, where the reconfigurable capabilities of FPGAS are not fully leveraged to maximize the overall system throughput. In this work, we present a systematic design space exploration methodology to maximize the throughput of an OpenCL-based FPGA accelerator for a given CNN model, considering the FPGA resource constraints such as on-chip memory, registers, computational resources and external memory bandwidth. The proposed methodology is demonstrated by optimizing two representative large-scale CNNs, AlexNet and VGG, on two Altera Stratix-V FPGA platforms, DE5-Net and P395-D8 boards, which have different hardware resources. We achieve a peak performance of 136.5 GOPS for convolution operation, and 117.8 GOPS for the entire VGG network that performs ImageNet classification on P395-D8 board.
KW - Convolutional neural networks
KW - FPGA
KW - OpenCL
KW - Optimization
UR - http://www.scopus.com/inward/record.url?scp=84966471227&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84966471227&partnerID=8YFLogxK
U2 - 10.1145/2847263.2847276
DO - 10.1145/2847263.2847276
M3 - Conference contribution
AN - SCOPUS:84966471227
SN - 9781450338561
SP - 16
EP - 25
BT - FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
PB - Association for Computing Machinery, Inc
ER -