Threshold logic in a flash

Ankit Wagle, Gian Singh, Jinghua Yang, Sunil Khatri, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper describes a novel design of a threshold logic gate (a binary perceptron) and its implementation as a standard cell. This new cell structure, referred to as flash threshold logic (FTL), uses floating gate (flash) transistors to realize the weights associated with a threshold function. The threshold voltages of the flash transistors serve as proxy for the weights. An FTL cell can be equivalently viewed as a multi-input, edge-triggered flipflop which computes a threshold function on a clock edge. Consequently it can used in automatic synthesis of ASICs. The use of flash transistors in the FTL cell allows programming of the weights after fabrication, thereby preventing discovery of its function by a foundry or by reverse engineering. This paper focuses on the design and characteristics of the FTL cell. We present a novel method for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm. The algorithm is further extended to select weights to maximize the robustness of the design in the presence of process variations. The FTL circuit was designed in 40nm technology and simulations with layout-extracted parasitics included, demonstrate significant improvements in area (79.7%), power (61.1%), and performance (42.5%) when compared to the equivalent implementations of the same function in conventional static CMOS design. Weight selection targeting robustness is demonstrated using Monte Carlo simulations. The paper also shows how FTL cells can be used for fixing timing errors after fabrication.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages550-558
Number of pages9
ISBN (Electronic)9781538666487
DOIs
StatePublished - Nov 2019
Event37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates
Duration: Nov 17 2019Nov 20 2019

Publication series

NameProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

Conference

Conference37th IEEE International Conference on Computer Design, ICCD 2019
CountryUnited Arab Emirates
CityAbu Dhabi
Period11/17/1911/20/19

Keywords

  • Flash
  • Floating Gate
  • High Performance
  • Low Power
  • Perceptron
  • Threshold Logic

ASJC Scopus subject areas

  • Information Systems and Management
  • Computer Networks and Communications
  • Control and Optimization
  • Hardware and Architecture

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  • Cite this

    Wagle, A., Singh, G., Yang, J., Khatri, S., & Vrudhula, S. (2019). Threshold logic in a flash. In Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019 (pp. 550-558). [8988749] (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD46524.2019.00081