9 Scopus citations

Abstract

Three-Dimensional NAND flash technology is one of the most competitive integrated solutions for the high-volume massive data storage. So far, there are few investigations on how to use 3-D NAND flash for in-memory computing in the neural network accelerator. In this brief, we propose using the 3-D vertical channel NAND array architecture to implement the vector-matrix multiplication (VMM) with for the first time. Based on the array-level SPICE simulation, the bias condition including the selector layer and the unselected layers is optimized to achieve high computation accuracy of VMM. Since the VMM can be performed layer by layer in a 3-D NAND array, the read-out latency is largely improved compared to the conventional single-cell read-out operation. The impact of device-to-device variation on the computation accuracy is also analyzed.

Original languageEnglish (US)
Article number8571188
Pages (from-to)988-991
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number4
DOIs
StatePublished - Apr 2019

Keywords

  • 3-D NAND flash
  • neural network
  • vector-matrix multiplication (VMM)
  • weighted sum

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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