This article proposes to tackle the high chip temperature problem caused by a few thermal hot spots in a processor using a different approach. In addition to using cooling mechanisms, such as metal heat sinks or fans, and dynamic thermal/power management solutions, this work investigates a new, fine-grained spot cooling technique for processors using thermoelectric generators (TEGs) and coolers (TECs) at the processor microarchitecture level. The proposed approach reduces the temperature of hot spots with TECs that are powered by TEG-based processor waste heat harvesting. The approach is sustainable in that it does not require additional power input for spot cooling while being able to lower the total chip temperature. The design takes advantage of two critical observations of processor temperature distribution and reliability. First, the temperature difference between the hot spots and cooler areas is typically tens of degrees on modern processors. Second, the reliability of the entire chip is limited by the highest of the hot spot temperatures. This presents an opportunity such that if we can maintain the same chip reliability by keeping the hot spot temperature constant or lower while allowing the temperature of the cooler chip area to increase to, but not exceed, the hot spot temperature, we would be able to harvest the processor waste heat without degrading reliability. We also show that the harvested electrical energy can be used to lower the temperature of processor hot spots, therefore reducing the overall chip temperature and improving reliability. The temperature evaluation results based on an open source processor temperature simulation tool-HotSpot 5.02-show that the proposed technique can effectively lower the chip temperature by an average of 7.7°C across the benchmarks studied in this paper. This temperature reduction corresponds to 29% meantime-to-failure MTTFEM and 5.7% MTTFTDDB reliability improvements. The proposed approach is a novel, self-sustaining spot cooling technique that does not require any power input and can effectively reduce the overall chip temperature for improved chip reliability.

Original languageEnglish (US)
Title of host publicationProceedings of the 15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)9781467381215
StatePublished - Jul 20 2016
Event15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2016 - Las Vegas, United States
Duration: May 31 2016Jun 3 2016


Other15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2016
CountryUnited States
CityLas Vegas


  • chip reliability
  • Processor hot spot mitigation
  • thermoelectric-based cooling
  • waste heat harvesting

ASJC Scopus subject areas

  • Fluid Flow and Transfer Processes
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Mechanics of Materials

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