The Progressive Learning Platform for computer engineering

David Jakob Fritz, Wira Mulia, Sohum Sohoni, Kerri S. Kearney, Mwarumba Mwavita

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper describes the Progressive Learning Platform (PLP), a system designed to facilitate computer engineering education while decreasing the overhead costs and learning curve associated with existing solutions. The PLP system is a System on a Chip design with accompanying tools reflecting a contemporary CPU architecture. It is unique in that it can be used in a number of courses (Digital Logic Design, Microcomputer Principles, Computer Architecture, Compilers, Embedded Systems) as students progress through a Computer Engineering curriculum. The system consists of a fully pipelined, MIPS like processor with surrounding support hardware. The support hardware includes a programmable interrupt controller, VGA controller and framebuffer, UART, memory controller, simple cache, timer, and GPIO hardware. All components are written in Verilog HDL, are open-source, and are freely available. To support the hardware components, a unified assembler, cycle accurate emulator, and board interface software package is included. The software is written in Java, works on Linux, Windows, and Mac OS, is open-source, and is freely available. With only a brief learning curve on the PLP system, students can work on course objectives immediately. The system and accompanying curriculum emphasize inter-and intra-team collaborative learning by compartmentalizing components of the design process used in lab to individual teams. The goal is to expose students to a less controlled environment representative of real-world design practice. Student teams are responsible for the design decisions of their assigned component, as well as ensuring that components are compatible for use in the larger, class-wide system. Other highlights of the PLP system are: a "hands-on? experience with real hardware early in the computer engineering curriculum, low overall cost for students and institutions, and cross-course application of concepts. The latter is of great importance since students often fail to see how concepts learned in one course apply to another. With an overarching system like PLP, where different aspects of it are taught and used in a variety of courses, student can make direct connections and see how concepts in computing are related. In this paper we present a case study of the PLP system in use in an undergraduate Computer Architecture course at Oklahoma State University. We also provide the rationale behind the development of each aspect of PLP and the expected impact on student learning, motivation, and retention.

Original languageEnglish (US)
JournalASEE Annual Conference and Exposition, Conference Proceedings
StatePublished - 2011
Externally publishedYes

Fingerprint

Students
Curricula
Computer architecture
Hardware
Computer hardware
Logic design
Computer hardware description languages
Controllers
Engineering education
Programmable logic controllers
Embedded systems
Software packages
Microcomputers
Interfaces (computer)
Program processors
Costs
Data storage equipment

ASJC Scopus subject areas

  • Engineering(all)

Cite this

The Progressive Learning Platform for computer engineering. / Fritz, David Jakob; Mulia, Wira; Sohoni, Sohum; Kearney, Kerri S.; Mwavita, Mwarumba.

In: ASEE Annual Conference and Exposition, Conference Proceedings, 2011.

Research output: Contribution to journalArticle

Fritz, David Jakob ; Mulia, Wira ; Sohoni, Sohum ; Kearney, Kerri S. ; Mwavita, Mwarumba. / The Progressive Learning Platform for computer engineering. In: ASEE Annual Conference and Exposition, Conference Proceedings. 2011.
@article{335324df01d64895930fbb53ac2f76b4,
title = "The Progressive Learning Platform for computer engineering",
abstract = "This paper describes the Progressive Learning Platform (PLP), a system designed to facilitate computer engineering education while decreasing the overhead costs and learning curve associated with existing solutions. The PLP system is a System on a Chip design with accompanying tools reflecting a contemporary CPU architecture. It is unique in that it can be used in a number of courses (Digital Logic Design, Microcomputer Principles, Computer Architecture, Compilers, Embedded Systems) as students progress through a Computer Engineering curriculum. The system consists of a fully pipelined, MIPS like processor with surrounding support hardware. The support hardware includes a programmable interrupt controller, VGA controller and framebuffer, UART, memory controller, simple cache, timer, and GPIO hardware. All components are written in Verilog HDL, are open-source, and are freely available. To support the hardware components, a unified assembler, cycle accurate emulator, and board interface software package is included. The software is written in Java, works on Linux, Windows, and Mac OS, is open-source, and is freely available. With only a brief learning curve on the PLP system, students can work on course objectives immediately. The system and accompanying curriculum emphasize inter-and intra-team collaborative learning by compartmentalizing components of the design process used in lab to individual teams. The goal is to expose students to a less controlled environment representative of real-world design practice. Student teams are responsible for the design decisions of their assigned component, as well as ensuring that components are compatible for use in the larger, class-wide system. Other highlights of the PLP system are: a {"}hands-on? experience with real hardware early in the computer engineering curriculum, low overall cost for students and institutions, and cross-course application of concepts. The latter is of great importance since students often fail to see how concepts learned in one course apply to another. With an overarching system like PLP, where different aspects of it are taught and used in a variety of courses, student can make direct connections and see how concepts in computing are related. In this paper we present a case study of the PLP system in use in an undergraduate Computer Architecture course at Oklahoma State University. We also provide the rationale behind the development of each aspect of PLP and the expected impact on student learning, motivation, and retention.",
author = "Fritz, {David Jakob} and Wira Mulia and Sohum Sohoni and Kearney, {Kerri S.} and Mwarumba Mwavita",
year = "2011",
language = "English (US)",
journal = "ASEE Annual Conference and Exposition, Conference Proceedings",
issn = "2153-5965",

}

TY - JOUR

T1 - The Progressive Learning Platform for computer engineering

AU - Fritz, David Jakob

AU - Mulia, Wira

AU - Sohoni, Sohum

AU - Kearney, Kerri S.

AU - Mwavita, Mwarumba

PY - 2011

Y1 - 2011

N2 - This paper describes the Progressive Learning Platform (PLP), a system designed to facilitate computer engineering education while decreasing the overhead costs and learning curve associated with existing solutions. The PLP system is a System on a Chip design with accompanying tools reflecting a contemporary CPU architecture. It is unique in that it can be used in a number of courses (Digital Logic Design, Microcomputer Principles, Computer Architecture, Compilers, Embedded Systems) as students progress through a Computer Engineering curriculum. The system consists of a fully pipelined, MIPS like processor with surrounding support hardware. The support hardware includes a programmable interrupt controller, VGA controller and framebuffer, UART, memory controller, simple cache, timer, and GPIO hardware. All components are written in Verilog HDL, are open-source, and are freely available. To support the hardware components, a unified assembler, cycle accurate emulator, and board interface software package is included. The software is written in Java, works on Linux, Windows, and Mac OS, is open-source, and is freely available. With only a brief learning curve on the PLP system, students can work on course objectives immediately. The system and accompanying curriculum emphasize inter-and intra-team collaborative learning by compartmentalizing components of the design process used in lab to individual teams. The goal is to expose students to a less controlled environment representative of real-world design practice. Student teams are responsible for the design decisions of their assigned component, as well as ensuring that components are compatible for use in the larger, class-wide system. Other highlights of the PLP system are: a "hands-on? experience with real hardware early in the computer engineering curriculum, low overall cost for students and institutions, and cross-course application of concepts. The latter is of great importance since students often fail to see how concepts learned in one course apply to another. With an overarching system like PLP, where different aspects of it are taught and used in a variety of courses, student can make direct connections and see how concepts in computing are related. In this paper we present a case study of the PLP system in use in an undergraduate Computer Architecture course at Oklahoma State University. We also provide the rationale behind the development of each aspect of PLP and the expected impact on student learning, motivation, and retention.

AB - This paper describes the Progressive Learning Platform (PLP), a system designed to facilitate computer engineering education while decreasing the overhead costs and learning curve associated with existing solutions. The PLP system is a System on a Chip design with accompanying tools reflecting a contemporary CPU architecture. It is unique in that it can be used in a number of courses (Digital Logic Design, Microcomputer Principles, Computer Architecture, Compilers, Embedded Systems) as students progress through a Computer Engineering curriculum. The system consists of a fully pipelined, MIPS like processor with surrounding support hardware. The support hardware includes a programmable interrupt controller, VGA controller and framebuffer, UART, memory controller, simple cache, timer, and GPIO hardware. All components are written in Verilog HDL, are open-source, and are freely available. To support the hardware components, a unified assembler, cycle accurate emulator, and board interface software package is included. The software is written in Java, works on Linux, Windows, and Mac OS, is open-source, and is freely available. With only a brief learning curve on the PLP system, students can work on course objectives immediately. The system and accompanying curriculum emphasize inter-and intra-team collaborative learning by compartmentalizing components of the design process used in lab to individual teams. The goal is to expose students to a less controlled environment representative of real-world design practice. Student teams are responsible for the design decisions of their assigned component, as well as ensuring that components are compatible for use in the larger, class-wide system. Other highlights of the PLP system are: a "hands-on? experience with real hardware early in the computer engineering curriculum, low overall cost for students and institutions, and cross-course application of concepts. The latter is of great importance since students often fail to see how concepts learned in one course apply to another. With an overarching system like PLP, where different aspects of it are taught and used in a variety of courses, student can make direct connections and see how concepts in computing are related. In this paper we present a case study of the PLP system in use in an undergraduate Computer Architecture course at Oklahoma State University. We also provide the rationale behind the development of each aspect of PLP and the expected impact on student learning, motivation, and retention.

UR - http://www.scopus.com/inward/record.url?scp=85029050575&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85029050575&partnerID=8YFLogxK

M3 - Article

JO - ASEE Annual Conference and Exposition, Conference Proceedings

JF - ASEE Annual Conference and Exposition, Conference Proceedings

SN - 2153-5965

ER -