The predictive technology model in the late silicon era and beyond

Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi Chao Wang, Wenping Wang, Wei Zhao

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires the Predictive Technology Model (PTM) for future technology generations, including nanoscale CMOS and post-silicon devices. This paper presents a comprehensive set of predictive modeling developments. Starting from the PTM of traditional CMOS devices, it extends to CMOS alternatives at the end of the silicon roadmap, such as strained Si, high-k/metal gate, and FinFET devices. The impact of process variation and the aging effect is further captured by modeling the device parameters under the influence. Beyond the silicon roadmap, the PTM outreaches to revolutionary devices, especially carbon-based transistor and interconnect, in order to support explorative design research. Overall, these predictive device models enable early stage design exploration with increasing technology diversity, helping shed light on the opportunities and challenges in the nanoelectronics era.

Original languageEnglish (US)
Pages (from-to)305-401
Number of pages97
JournalFoundations and Trends in Electronic Design Automation
Volume3
Issue number4
DOIs
StatePublished - 2009

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design

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