TY - JOUR
T1 - The impact of NBTI effect on combinational circuit
T2 - Modeling, simulation, and analysis
AU - Wang, Wenping
AU - Yang, Shengqi
AU - Bhardwaj, Sarvesh
AU - Vrudhula, Sarma
AU - Liu, Frank
AU - Cao, Yu
N1 - Funding Information:
Manuscript received August 02, 2007; revised May 13, 2008. First published May 29, 2009; current version published January 20, 2010. This work was supported by the Gigascale Systems Research Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program, in part by the SRC, in part by Task 1354, and in part by the National Science Foundation (NSF) under Grant EEC-9523338.
PY - 2010/2
Y1 - 2010/2
N2 - Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5 for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.
AB - Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5 for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.
KW - Duty cycle
KW - Input pattern
KW - Negative bias temperature instability (NBTI)
KW - Performance degradation
KW - Speed
KW - Supply voltage
KW - Temperature
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U2 - 10.1109/TVLSI.2008.2008810
DO - 10.1109/TVLSI.2008.2008810
M3 - Article
AN - SCOPUS:75549089060
SN - 1063-8210
VL - 18
SP - 173
EP - 183
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 2
M1 - 5031899
ER -