The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays

Yuri Tkachev, Jong Won Yoo, Alexander Kotov, Lawrence T. Clark, Keith Holbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratios and FG channel parameters, have only a minor effect on Verase variability.

Original languageEnglish (US)
Title of host publication2018 IEEE 10th International Memory Workshop, IMW 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538652473
DOIs
Publication statusPublished - Jun 19 2018
Event10th IEEE International Memory Workshop, IMW 2018 - Kyoto, Japan
Duration: May 13 2018May 16 2018

Other

Other10th IEEE International Memory Workshop, IMW 2018
CountryJapan
CityKyoto
Period5/13/185/16/18

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Keywords

  • Flash memory
  • floating gate
  • split-gate memory cell
  • SuperFlash technology
  • variability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials

Cite this

Tkachev, Y., Yoo, J. W., Kotov, A., Clark, L. T., & Holbert, K. (2018). The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays. In 2018 IEEE 10th International Memory Workshop, IMW 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMW.2018.8388855