The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays

Yuri Tkachev; Jong Won Yoo; Alexander Kotov; Lawrence T. Clark; Keith Holbert

doi:10.1109/IMW.2018.8388855

The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays

Yuri Tkachev, Jong Won Yoo, Alexander Kotov, Lawrence T. Clark, Keith Holbert

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratios and FG channel parameters, have only a minor effect on Verase variability.

Original language	English (US)
Title of host publication	2018 IEEE 10th International Memory Workshop, IMW 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538652473
DOIs	https://doi.org/10.1109/IMW.2018.8388855
State	Published - Jun 19 2018
Event	10th IEEE International Memory Workshop, IMW 2018 - Kyoto, Japan Duration: May 13 2018 → May 16 2018

Publication series

Name	2018 IEEE 10th International Memory Workshop, IMW 2018

Other

Other	10th IEEE International Memory Workshop, IMW 2018
Country/Territory	Japan
City	Kyoto
Period	5/13/18 → 5/16/18

Keywords

Flash memory
SuperFlash technology
floating gate
split-gate memory cell
variability

ASJC Scopus subject areas

Hardware and Architecture
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/IMW.2018.8388855

Cite this

Tkachev, Y., Yoo, J. W., Kotov, A., Clark, L. T., & Holbert, K. (2018). The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays. In 2018 IEEE 10th International Memory Workshop, IMW 2018 (pp. 1-4). (2018 IEEE 10th International Memory Workshop, IMW 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMW.2018.8388855

The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays. / Tkachev, Yuri; Yoo, Jong Won; Kotov, Alexander et al.
2018 IEEE 10th International Memory Workshop, IMW 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 IEEE 10th International Memory Workshop, IMW 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tkachev, Y, Yoo, JW, Kotov, A, Clark, LT & Holbert, K 2018, The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays. in 2018 IEEE 10th International Memory Workshop, IMW 2018. 2018 IEEE 10th International Memory Workshop, IMW 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 10th IEEE International Memory Workshop, IMW 2018, Kyoto, Japan, 5/13/18. https://doi.org/10.1109/IMW.2018.8388855

@inproceedings{8d24783da2f14cac8cf166a332e9f54d,

title = "The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays",

abstract = "We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratios and FG channel parameters, have only a minor effect on Verase variability.",

keywords = "Flash memory, SuperFlash technology, floating gate, split-gate memory cell, variability",

author = "Yuri Tkachev and Yoo, {Jong Won} and Alexander Kotov and Clark, {Lawrence T.} and Keith Holbert",

year = "2018",

month = jun,

day = "19",

doi = "10.1109/IMW.2018.8388855",

language = "English (US)",

series = "2018 IEEE 10th International Memory Workshop, IMW 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2018 IEEE 10th International Memory Workshop, IMW 2018",

note = "10th IEEE International Memory Workshop, IMW 2018 ; Conference date: 13-05-2018 Through 16-05-2018",

}

TY - GEN

T1 - The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays

AU - Tkachev, Yuri

AU - Yoo, Jong Won

AU - Kotov, Alexander

AU - Clark, Lawrence T.

AU - Holbert, Keith

PY - 2018/6/19

Y1 - 2018/6/19

N2 - We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratios and FG channel parameters, have only a minor effect on Verase variability.

AB - We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratios and FG channel parameters, have only a minor effect on Verase variability.

KW - Flash memory

KW - SuperFlash technology

KW - floating gate

KW - split-gate memory cell

KW - variability

UR - http://www.scopus.com/inward/record.url?scp=85050025872&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85050025872&partnerID=8YFLogxK

U2 - 10.1109/IMW.2018.8388855

DO - 10.1109/IMW.2018.8388855

M3 - Conference contribution

AN - SCOPUS:85050025872

T3 - 2018 IEEE 10th International Memory Workshop, IMW 2018

SP - 1

EP - 4

BT - 2018 IEEE 10th International Memory Workshop, IMW 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 10th IEEE International Memory Workshop, IMW 2018

Y2 - 13 May 2018 through 16 May 2018

ER -

The Analysis of Erase Voltage Variability in 70-nm Split-Gate Flash Memory Arrays

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this