Test selection based on high level fault simulation for mixed-signal systems

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingChapter

6 Citations (Scopus)

Abstract

Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE VLSI Test Symposium
Place of PublicationLos Alamitos, CA, United States
PublisherIEEE
Pages149-154
Number of pages6
StatePublished - 2000
Externally publishedYes
Event18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can
Duration: Apr 30 2000May 4 2000

Other

Other18th IEEE VLSI Test Symposium (VTS-2000)
CityMontreal, Que, Can
Period4/30/005/4/00

Fingerprint

Signal systems
Signal receivers
Simulators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ozev, S., & Orailoglu, A. (2000). Test selection based on high level fault simulation for mixed-signal systems. In Proceedings of the IEEE VLSI Test Symposium (pp. 149-154). Los Alamitos, CA, United States: IEEE.

Test selection based on high level fault simulation for mixed-signal systems. / Ozev, Sule; Orailoglu, Alex.

Proceedings of the IEEE VLSI Test Symposium. Los Alamitos, CA, United States : IEEE, 2000. p. 149-154.

Research output: Chapter in Book/Report/Conference proceedingChapter

Ozev, S & Orailoglu, A 2000, Test selection based on high level fault simulation for mixed-signal systems. in Proceedings of the IEEE VLSI Test Symposium. IEEE, Los Alamitos, CA, United States, pp. 149-154, 18th IEEE VLSI Test Symposium (VTS-2000), Montreal, Que, Can, 4/30/00.
Ozev S, Orailoglu A. Test selection based on high level fault simulation for mixed-signal systems. In Proceedings of the IEEE VLSI Test Symposium. Los Alamitos, CA, United States: IEEE. 2000. p. 149-154
Ozev, Sule ; Orailoglu, Alex. / Test selection based on high level fault simulation for mixed-signal systems. Proceedings of the IEEE VLSI Test Symposium. Los Alamitos, CA, United States : IEEE, 2000. pp. 149-154
@inbook{f704f23a65cc44adb19d0de597b1d7fc,
title = "Test selection based on high level fault simulation for mixed-signal systems",
abstract = "Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.",
author = "Sule Ozev and Alex Orailoglu",
year = "2000",
language = "English (US)",
pages = "149--154",
booktitle = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE",

}

TY - CHAP

T1 - Test selection based on high level fault simulation for mixed-signal systems

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 2000

Y1 - 2000

N2 - Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

AB - Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

UR - http://www.scopus.com/inward/record.url?scp=0033733913&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033733913&partnerID=8YFLogxK

M3 - Chapter

SP - 149

EP - 154

BT - Proceedings of the IEEE VLSI Test Symposium

PB - IEEE

CY - Los Alamitos, CA, United States

ER -