Abstract
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.
Original language | English (US) |
---|---|
Title of host publication | Proceedings of the IEEE VLSI Test Symposium |
Place of Publication | Los Alamitos, CA, United States |
Publisher | IEEE |
Pages | 149-154 |
Number of pages | 6 |
State | Published - 2000 |
Externally published | Yes |
Event | 18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can Duration: Apr 30 2000 → May 4 2000 |
Other
Other | 18th IEEE VLSI Test Symposium (VTS-2000) |
---|---|
City | Montreal, Que, Can |
Period | 4/30/00 → 5/4/00 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering