Test planning for mixed-signal SOCs with wrapped analog cores

Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE '05
Pages50-55
Number of pages6
VolumeI
DOIs
StatePublished - 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sehgal, A., Liu, F., Ozev, S., & Chakrabarty, K. (2005). Test planning for mixed-signal SOCs with wrapped analog cores. In Proceedings -Design, Automation and Test in Europe, DATE '05 (Vol. I, pp. 50-55). [1395528] https://doi.org/10.1109/DATE.2005.303

Test planning for mixed-signal SOCs with wrapped analog cores. / Sehgal, Anuja; Liu, Fang; Ozev, Sule; Chakrabarty, Krishnendu.

Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. p. 50-55 1395528.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sehgal, A, Liu, F, Ozev, S & Chakrabarty, K 2005, Test planning for mixed-signal SOCs with wrapped analog cores. in Proceedings -Design, Automation and Test in Europe, DATE '05. vol. I, 1395528, pp. 50-55, Design, Automation and Test in Europe, DATE '05, Munich, Germany, 3/7/05. https://doi.org/10.1109/DATE.2005.303
Sehgal A, Liu F, Ozev S, Chakrabarty K. Test planning for mixed-signal SOCs with wrapped analog cores. In Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I. 2005. p. 50-55. 1395528 https://doi.org/10.1109/DATE.2005.303
Sehgal, Anuja ; Liu, Fang ; Ozev, Sule ; Chakrabarty, Krishnendu. / Test planning for mixed-signal SOCs with wrapped analog cores. Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. pp. 50-55
@inproceedings{8f2cc005e84b442a87299ad9af9f1b43,
title = "Test planning for mixed-signal SOCs with wrapped analog cores",
abstract = "Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.",
author = "Anuja Sehgal and Fang Liu and Sule Ozev and Krishnendu Chakrabarty",
year = "2005",
doi = "10.1109/DATE.2005.303",
language = "English (US)",
isbn = "0769522882",
volume = "I",
pages = "50--55",
booktitle = "Proceedings -Design, Automation and Test in Europe, DATE '05",

}

TY - GEN

T1 - Test planning for mixed-signal SOCs with wrapped analog cores

AU - Sehgal, Anuja

AU - Liu, Fang

AU - Ozev, Sule

AU - Chakrabarty, Krishnendu

PY - 2005

Y1 - 2005

N2 - Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

AB - Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

UR - http://www.scopus.com/inward/record.url?scp=33646919808&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646919808&partnerID=8YFLogxK

U2 - 10.1109/DATE.2005.303

DO - 10.1109/DATE.2005.303

M3 - Conference contribution

AN - SCOPUS:33646919808

SN - 0769522882

SN - 9780769522883

VL - I

SP - 50

EP - 55

BT - Proceedings -Design, Automation and Test in Europe, DATE '05

ER -