Test application for analog/RF circuits with low computational burden

Ender Yilmaz, Sule Ozev

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

In this paper, we propose an adaptive test strategy that tailors the test sequence with respect to the properties of each individual instance of a circuit. Reducing the test set by analyzing the dropout patterns during characterization and eliminating the unnecessary tests has always been the approach for high volume production in the analog domain. However, once determined, the test set remains typically fixed for all devices. We propose to exploit the statistical diversity of the manufactured devices and adaptively eliminate tests that are determined to be unnecessary based on information obtained on the circuit under test. Test time information is incorporated in the method to yield short test time. The proposed methodology is computationally efficient and imposes very little overhead on the tester. We compare our results with other similar specification-based test reduction techniques for a low noise amplifier (LNA) circuit and an analog industrial circuit. Results show 85% test quality improvement for the same test time or 24% test time reduction for the same test quality for the LNA circuit. Moreover, near zero defective parts per million is achieved for the industrial circuit.

Original languageEnglish (US)
Article number6200445
Pages (from-to)968-979
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume31
Issue number6
DOIs
StatePublished - May 29 2012

Keywords

  • Adaptive test
  • analog/RF circuits
  • test compaction

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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