Tensile Ge/GeSn/Si Structure for CMOS Compatible Telecommunications Wavelengths

John Kouvetakis (Inventor)

Research output: Patent

Abstract

Germanium (Ge) has a direct band gap (E0) of 0.81 eV at room temperature; however, applying small perturbations to Ge can shift E0 to lower energies resulting in dramatically improved performance for semiconductor and telecommunication applications. Stressing Ge using tensile strain provides one means by which to lower its E0, but the current best method requires depositing the Ge on Silicon (Si) at relatively high temperatures and inducing stress through the subsequent contraction of the Si. While this process provides biaxial tensile strains as high as 0.25% in films as thick as 1 m, higher strain values are necessary for most optoelectronic applications, which require tunable E0. Furthermore, the thermal expansion process lacks precise strain control, offers limited maximum strain value (0.3%), and effectuates undesirable inter-diffusion of the elements across the Si-Ge heterojunction. Researchers at Arizona State University have developed an improved method for preparing tensile strained Ge on semiconductor substrates. Specifically, this method forms a tensile strained layer of Ge over a layer of Ge1-ySny deposited on a semiconductor substrate using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The tensile strained. The method functions to tune the strain of the Ge epilayer by varying the buffer composition. Potential Applications Semiconductor Electronics (e.g. high-speed transistors, back-end CMOS telecommunications, etc.) Optoelectronics (e.g. Optical Fiber Communications, Lasers, etc.) Benefits and Advantages Tunable Tensile Strains (between 0.15% and 0.45%) precise strain control for optoelectronic applications Increased Maximum Tensile Strain (high as 0.45% observed compared to 0.3%) necessary for viability in higher bands (e.g. U-Band) Operates at Substantially Lower Temperatures (growth occurs at 350-380C as opposed to 800-900C) reduces inter-diffusion of the elements across the Si-Ge heterojunction; CMOS compatible Offers High-Quality, Thermally Stable Tensile Strained Ge Layers (greater than 100 nm thick have been grown on Si(100) wafers) Exhibits Desirable Crystalline Geometry perfectly tetragonal structure, homogenous compositional and strain profiles, low threading dislocation densities and atomically planar surfaces; optimal for tuning applications Download original PDF
Original languageEnglish (US)
StatePublished - Dec 28 2006

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telecommunication
germanium
CMOS
silicon
wavelengths
heterojunctions
admixtures
viability
contraction
optical communication
thermal expansion
transistors
buffers
optical fibers
tuning
high speed
wafers
perturbation
shift
room temperature

Cite this

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title = "Tensile Ge/GeSn/Si Structure for CMOS Compatible Telecommunications Wavelengths",
abstract = "Germanium (Ge) has a direct band gap (E0) of 0.81 eV at room temperature; however, applying small perturbations to Ge can shift E0 to lower energies resulting in dramatically improved performance for semiconductor and telecommunication applications. Stressing Ge using tensile strain provides one means by which to lower its E0, but the current best method requires depositing the Ge on Silicon (Si) at relatively high temperatures and inducing stress through the subsequent contraction of the Si. While this process provides biaxial tensile strains as high as 0.25{\%} in films as thick as 1 m, higher strain values are necessary for most optoelectronic applications, which require tunable E0. Furthermore, the thermal expansion process lacks precise strain control, offers limited maximum strain value (0.3{\%}), and effectuates undesirable inter-diffusion of the elements across the Si-Ge heterojunction. Researchers at Arizona State University have developed an improved method for preparing tensile strained Ge on semiconductor substrates. Specifically, this method forms a tensile strained layer of Ge over a layer of Ge1-ySny deposited on a semiconductor substrate using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The tensile strained. The method functions to tune the strain of the Ge epilayer by varying the buffer composition. Potential Applications Semiconductor Electronics (e.g. high-speed transistors, back-end CMOS telecommunications, etc.) Optoelectronics (e.g. Optical Fiber Communications, Lasers, etc.) Benefits and Advantages Tunable Tensile Strains (between 0.15{\%} and 0.45{\%}) precise strain control for optoelectronic applications Increased Maximum Tensile Strain (high as 0.45{\%} observed compared to 0.3{\%}) necessary for viability in higher bands (e.g. U-Band) Operates at Substantially Lower Temperatures (growth occurs at 350-380C as opposed to 800-900C) reduces inter-diffusion of the elements across the Si-Ge heterojunction; CMOS compatible Offers High-Quality, Thermally Stable Tensile Strained Ge Layers (greater than 100 nm thick have been grown on Si(100) wafers) Exhibits Desirable Crystalline Geometry perfectly tetragonal structure, homogenous compositional and strain profiles, low threading dislocation densities and atomically planar surfaces; optimal for tuning applications Download original PDF",
author = "John Kouvetakis",
year = "2006",
month = "12",
day = "28",
language = "English (US)",
type = "Patent",

}

TY - PAT

T1 - Tensile Ge/GeSn/Si Structure for CMOS Compatible Telecommunications Wavelengths

AU - Kouvetakis, John

PY - 2006/12/28

Y1 - 2006/12/28

N2 - Germanium (Ge) has a direct band gap (E0) of 0.81 eV at room temperature; however, applying small perturbations to Ge can shift E0 to lower energies resulting in dramatically improved performance for semiconductor and telecommunication applications. Stressing Ge using tensile strain provides one means by which to lower its E0, but the current best method requires depositing the Ge on Silicon (Si) at relatively high temperatures and inducing stress through the subsequent contraction of the Si. While this process provides biaxial tensile strains as high as 0.25% in films as thick as 1 m, higher strain values are necessary for most optoelectronic applications, which require tunable E0. Furthermore, the thermal expansion process lacks precise strain control, offers limited maximum strain value (0.3%), and effectuates undesirable inter-diffusion of the elements across the Si-Ge heterojunction. Researchers at Arizona State University have developed an improved method for preparing tensile strained Ge on semiconductor substrates. Specifically, this method forms a tensile strained layer of Ge over a layer of Ge1-ySny deposited on a semiconductor substrate using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The tensile strained. The method functions to tune the strain of the Ge epilayer by varying the buffer composition. Potential Applications Semiconductor Electronics (e.g. high-speed transistors, back-end CMOS telecommunications, etc.) Optoelectronics (e.g. Optical Fiber Communications, Lasers, etc.) Benefits and Advantages Tunable Tensile Strains (between 0.15% and 0.45%) precise strain control for optoelectronic applications Increased Maximum Tensile Strain (high as 0.45% observed compared to 0.3%) necessary for viability in higher bands (e.g. U-Band) Operates at Substantially Lower Temperatures (growth occurs at 350-380C as opposed to 800-900C) reduces inter-diffusion of the elements across the Si-Ge heterojunction; CMOS compatible Offers High-Quality, Thermally Stable Tensile Strained Ge Layers (greater than 100 nm thick have been grown on Si(100) wafers) Exhibits Desirable Crystalline Geometry perfectly tetragonal structure, homogenous compositional and strain profiles, low threading dislocation densities and atomically planar surfaces; optimal for tuning applications Download original PDF

AB - Germanium (Ge) has a direct band gap (E0) of 0.81 eV at room temperature; however, applying small perturbations to Ge can shift E0 to lower energies resulting in dramatically improved performance for semiconductor and telecommunication applications. Stressing Ge using tensile strain provides one means by which to lower its E0, but the current best method requires depositing the Ge on Silicon (Si) at relatively high temperatures and inducing stress through the subsequent contraction of the Si. While this process provides biaxial tensile strains as high as 0.25% in films as thick as 1 m, higher strain values are necessary for most optoelectronic applications, which require tunable E0. Furthermore, the thermal expansion process lacks precise strain control, offers limited maximum strain value (0.3%), and effectuates undesirable inter-diffusion of the elements across the Si-Ge heterojunction. Researchers at Arizona State University have developed an improved method for preparing tensile strained Ge on semiconductor substrates. Specifically, this method forms a tensile strained layer of Ge over a layer of Ge1-ySny deposited on a semiconductor substrate using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The tensile strained. The method functions to tune the strain of the Ge epilayer by varying the buffer composition. Potential Applications Semiconductor Electronics (e.g. high-speed transistors, back-end CMOS telecommunications, etc.) Optoelectronics (e.g. Optical Fiber Communications, Lasers, etc.) Benefits and Advantages Tunable Tensile Strains (between 0.15% and 0.45%) precise strain control for optoelectronic applications Increased Maximum Tensile Strain (high as 0.45% observed compared to 0.3%) necessary for viability in higher bands (e.g. U-Band) Operates at Substantially Lower Temperatures (growth occurs at 350-380C as opposed to 800-900C) reduces inter-diffusion of the elements across the Si-Ge heterojunction; CMOS compatible Offers High-Quality, Thermally Stable Tensile Strained Ge Layers (greater than 100 nm thick have been grown on Si(100) wafers) Exhibits Desirable Crystalline Geometry perfectly tetragonal structure, homogenous compositional and strain profiles, low threading dislocation densities and atomically planar surfaces; optimal for tuning applications Download original PDF

M3 - Patent

ER -