Temporal sequential logic hardening by design with a low power delay element

Sandeep Shambhulingaiah, Lawrence T. Clark, Thomas J. Mozdzen, Nathan D. Hindman, Srivatsan Chella, Keith Holbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to mask long transients, which would otherwise limit the circuit hardness. Two FF layouts using the proposed delay element are used in synthesis and auto-place and route experiments to confirm overall power, performance, and density. The first (interleaved) version uses a multi-bit cell interleaving the constituent circuits of four FFs. The second (inline) version interleaves the master and slave circuits to achieve high density while maintaining adequate critical node separation. The latter is shown to be more power efficient and the former is more robust to multiple node collection.

Original languageEnglish (US)
Title of host publicationRADECS 2011 - 12th European Conference on Radiation and Its Effects on Component and Systems, Conference Proceedings
Pages144-149
Number of pages6
DOIs
StatePublished - Dec 1 2011
Event12th European Conference on Radiation and Its Effects on Component and Systems, RADECS 2011 - Sevilla, Spain
Duration: Sep 19 2011Sep 23 2011

Publication series

NameProceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Other

Other12th European Conference on Radiation and Its Effects on Component and Systems, RADECS 2011
CountrySpain
CitySevilla
Period9/19/119/23/11

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Keywords

  • Radiation hardening by design
  • flip-flop
  • sequential logic circuits
  • single event transient
  • single event upset

ASJC Scopus subject areas

  • Radiation
  • Electrical and Electronic Engineering

Cite this

Shambhulingaiah, S., Clark, L. T., Mozdzen, T. J., Hindman, N. D., Chella, S., & Holbert, K. (2011). Temporal sequential logic hardening by design with a low power delay element. In RADECS 2011 - 12th European Conference on Radiation and Its Effects on Component and Systems, Conference Proceedings (pp. 144-149). [6131300] (Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS). https://doi.org/10.1109/RADECS.2011.6131300