TY - GEN
T1 - Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU
AU - Kumar, Sushil
AU - Chellappa, Srivatsan
AU - Clark, Lawrence T.
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.
AB - Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.
KW - Flip-Flop
KW - multiple node charge collection
KW - single event transient
KW - single event upset
KW - temporal hardening
KW - triple mode redundancy
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U2 - 10.1109/ISCAS.2015.7168758
DO - 10.1109/ISCAS.2015.7168758
M3 - Conference contribution
AN - SCOPUS:84946235555
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 814
EP - 817
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -