Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU

Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations


Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781479983919
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015


OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015


  • Flip-Flop
  • multiple node charge collection
  • single event transient
  • single event upset
  • temporal hardening
  • triple mode redundancy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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