Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU

Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages814-817
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Fingerprint

Flip flop circuits
Sequential circuits
Shift registers
Foundries
Redundancy
Macros
Hardening

Keywords

  • Flip-Flop
  • multiple node charge collection
  • single event transient
  • single event upset
  • temporal hardening
  • triple mode redundancy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kumar, S., Chellappa, S., & Clark, L. T. (2015). Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 814-817). [7168758] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168758

Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. / Kumar, Sushil; Chellappa, Srivatsan; Clark, Lawrence T.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 814-817 7168758.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kumar, S, Chellappa, S & Clark, LT 2015, Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7168758, Institute of Electrical and Electronics Engineers Inc., pp. 814-817, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7168758
Kumar S, Chellappa S, Clark LT. Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. p. 814-817. 7168758 https://doi.org/10.1109/ISCAS.2015.7168758
Kumar, Sushil ; Chellappa, Srivatsan ; Clark, Lawrence T. / Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. pp. 814-817
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